Methods of controlling formation of metal silicide regions,...

Details Methods of controlling formation of metal silicide regions,... Methods of controlling formation of metal silicide regions,...

2002-11-25

2004-11-09

Kang, Donghee (Department: 2811)

Semiconductor device manufacturing: process

With measuring or testing

Optical characteristic sensed

C438S014000, C438S649000, C438S651000, C438S755000, C374S126000, C374S128000, C374S178000

Reexamination Certificate

active

06815235

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to various methods of controlling the formation of metal silicide regions, and a system for performing same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating performance of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. Moreover, the density of such transistors on a wafer per unit area has dramatically increased as a result of, among other things, the reduction in feature sizes, and an overall desire to minimize the size of various integrated circuit products.
By way of background, modern integrated circuit devices, e.g., microprocessors. ASICs, memory devices, etc., are comprised of millions of field effect transistors formed on a semiconducting substrate, such as silicon. The substrate may be doped with either N-type or P-type dopant materials. An illustrative field effect transistor
10
, as shown in
FIG. 1
, may have a doped polycrystalline silicon (polysilicon) gate electrode
14
formed above a gate insulation layer
16
. The gate electrode
14
and the gate insulation layer
16
may be separated from doped source/drain regions
22
of the transistor
10
by a dielectric sidewall spacer
20
. The source/drain regions
22
for the transistor
10
may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g., arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the substrate
11
. Shallow trench isolation regions
18
may be provided to isolate the transistor
10
electrically from neighboring semiconductor devices, such as other transistors (not shown). Additionally, although not depicted in
FIG. 1
, a typical integrated circuit product is comprised of a plurality of conductive interconnections, such as conductive lines and conductive contacts or vias, positioned in multiple layers of insulating material formed above the substrate. These conductive interconnections allow electrical signals to propagate between the transistors formed above the substrate.
The gate electrode
14
has a critical dimension
12
, i.e., gate length, that approximately corresponds to the channel length
13
of the device when the transistor
10
is operational. Thus, it is very important that the critical dimension
12
of the gate electrode
14
be formed very accurately. Even small errors in the critical dimension
12
of the gate electrode
14
can result in the failure of the finished product to meet certain target electrical performance characteristics, e.g., switching speed, leakage current, etc. Of course, the critical dimension
12
of the gate electrode
14
is but one example of a feature that must be formed very accurately in modem semiconductor manufacturing operations. Other examples include, but are not limited to, conductive lines, openings in insulating layers to allow subsequent formation of a conductive interconnection, i.e., a conductive line or contact, therein, etc.
Also depicted in
FIG. 1
are a plurality of metal silicide regions
17
that are formed above the gate electrode
14
and the source/drain regions
22
. In general, one purpose of the metal silicide regions
17
is to reduce contact resistance and thereby enhance various operating characteristics of the transistor
10
and integrated circuit products, e.g., microprocessors, incorporating such transistors
10
. The metal silicide regions
17
may be comprised of a variety of different materials, e.g., cobalt silicide, titanium silicide, nickel silicide, platinum silicide, tantalum silicide, tungsten silicide, etc.
The metal silicide regions
17
may be formed by a variety of known techniques. One illustrative process flow for forming the metal silicide regions
17
is depicted in
FIGS. 2A-2C
. Initially, as shown in
FIG. 2A
, a layer of refractory metal
21
is deposited above the gate electrode
14
and the source/drain regions
22
. Thereafter, one or more anneal processes are performed to convert portions of the layer of refractory metal
21
in contact with the silicon-containing gate electrode
14
and source/drain regions
22
into the metal silicide regions
17
, as indicated in FIG.
2
B. Then, a wet chemical process is performed to remove unreacted portions of the layer of refractory metal
21
, as shown in FIG.
2
C.
Referring back to
FIG. 1
, using current-day technology, the channel length
13
of modern transistors may be approximately 120-180 nm, and further reductions are planned in the future. The reduction in the channel length
13
of the transistor
10
also requires a reduction in the physical size of other components of the transistor
10
. For example, the depth of the source/drain regions
22
is also reduced along with the length
12
of the gate electrode
14
. As a result of the dramatic reduction of device dimensions, other aspects of the transistor
10
may act to limit the performance characteristics of the transistor. Stated another way, the performance of the transistor
10
may not be limited solely by the channel length
13
of the transistor
10
, but rather by the RC-time delay associated with the propagation of electrical signals in an integrated circuit device and within the transistor
10
. For example, delays associated with the propagation of an electrical signal along the width, i.e., into the drawing page, of the gate electrode
14
(to turn the transistor “ON”) may act to limit one or more operating characteristics of the transistor
10
. Similarly, signal propagation may be limited through the source/drain regions
22
of the transistor
10
. However, the thickness of metal silicide regions
17
on the source/drain regions
22
must be limited so as not to consume too much of the underlying source/drain regions
22
during the formation process.
In some cases, the process parameters used in forming metal silicide regions
17
, e.g., anneal temperatures and duration, the duration of wet chemical processes, etc., may be determined by performing various tests on a number of test wafers. In other cases, e.g., removal of unreacted refractory metal
21
, a wet chemical process is performed for a duration that is assumed to be sufficient for the maximum anticipated thickness of the originally formed layer of refractory metal
21
. However, the duration of the wet chemical process determined using this “worst case” type approach may unduly consume other components of the transistor
10
if the layer of refractory metal
21
is thinner than the anticipated “worst-case” thickness. For example, depending upon the composition of the material used for the side-wall spacers
20
, if the wet chemical process is performed for too long of a duration, it may consume too much of the sidewall spacers
20
. As another example, excessive etch time may consume some of the metal silicide regions
17
.
Additionally, the anneal processes performed to form the metal silicide regions
17
is typically a timed process that is performed for the specified duration set by the particular process flow. Similarly, the wet chemical process performed to remove the unreacted refractory metal is also a timed process. Such fixed, inflexible proce

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