Methods of biasing a multi-level-cell memory

Details Methods of biasing a multi-level-cell memory Methods of biasing a multi-level-cell memory

2007-04-27

2009-06-16

Phung, Anh (Department: 2824)

Static information storage and retrieval

Floating gate

Multiple values

C365S185180

Reexamination Certificate

active

07548458

ABSTRACT:
Methods are described for double-side-bias of multi-level-cell memory devices comprising a NAND array that comprises a plurality of charge trapping memory cells. A memory device is programmed by a double-side-bias electron injection technique and is erased by a double-side-bias hole injection technique. Each charge trapping memory cell includes 2nlogic states, such as four binary logic states of a logic 00 state, a logic 01 state, a logic 10 state and a logic 11 state. The memory device can be programmed by a double-side-bias multi-level-cell program method either with a variable DSB (Vd/Vs) voltage or with a variable gate bias voltage Vg.

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