Methods, media, and means for forming asynchronous logic...

Details Methods, media, and means for forming asynchronous logic... Methods, media, and means for forming asynchronous logic...

2007-05-24

2010-06-01

Phan, Thai (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Modeling by mathematical expression

C703S014000, C716S030000, C326S041000

Reexamination Certificate

active

07729893

ABSTRACT:
Methods, media, and means for forming asynchronous logic networks are provided. In some embodiments, methods for forming an asynchronous logic network are provided. The methods include: receiving a logic network including vertices and signals, wherein the vertices include vertices with multiple output signals; determining a set of signals of the signals included in the logic network to be covered; selecting at least one vertex in the logic network to cover each signal in the set of signals; replacing the at least one selected vertex with a robust vertex; and replacing at least one non-selected vertex with a relaxed vertex.

REFERENCES:
patent: 2003/0165158 (2003-09-01), Davies et al.
patent: 2006/0120189 (2006-06-01), Beerel et al.
patent: 2007/0164785 (2007-07-01), He
patent: 2007/0300203 (2007-12-01), Jeong et al.
Brej, C. F., “Early Output Logic and Anti-Tokens”, PhD thesis, University of Manchester, 2005.
Brent, R.P. et al., “A regular layout for parallel adders,” IEEE Trans. Comput., 1982.
Burns, S. M., “General conditions for the decomposition of state holding elements”, In Proc. Int. Symp. Asynchronous Circuits and System, 1996, pp. 48-57.
Constantinescu, C., “Trends and challenges in VLSI circuit reliability,” IEEE Micro, 2003, 23(4):14-99.
International Search Report and Written Opinion issued for corresponding International Patent Application No. PCT/US2007/012472.
Cortadella, J., “Decomposition and technology mapping of speed-independent circuits using Boolean relations,” IEEE Trans. Computer-Aided Des. lntegr. Circuits Syst., 1999, 18(9):1221-1236.
David, I. et al., “An efficient implementation of boolean functions as self-timed circuits,” IEEE Trans. Comput., 1992, 41(1):2-11.
De Micheli, G. et al., “Synthesis and Optimization of Digital Circuits,” McGraw Hill, 1994.
Fant, K.M., “Logically-Determined Design,” John Wiley & Sons, 2005.
Folco, B. et al., “Technology mapping for area optimized quasi delay insensitive circuits,” In Proc. IFIP Conf. Very Large Scale Integration Systems, 2005.
Jeong C. et al., “Optimal technology mapping and cell merger for asynchronous threshold networks,” In Proc. Int. Symp. Asynchronous Circuits and Systems, 2006, pp. 128-137.
Jeong et al., “Optimization of robust asynchronous circuits by local input completeness relaxation,” In Asia and South Pacific Des. Autom. Conf., 2007.
Jeong, C. et al., “Optimization for Timing-Robust Asynchronous Circuits Based on Eager Evaluation,” Presented at International Workshop on Logic Synthesis (IWLS), 2007.
Karaki, N., “Asynchronous Design: An Enabler for Flexible Microelectronics,” Proceedings 12th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2006, Mar. 13-15, 2006.
Kondratyev, A. et al., “Checking delay-insensitivity: 104 gates and beyond,” In Proc. Int. Symp. Asynchronous Circuits and Systems, 2002, pp. 149-157.
Kondratyev, A. et al., “Design of asynchronous circuits using synchronous CAD tools,” IEEE Design & Test of Computers, 2002, 19(4):107-117.
Ligthart, M. et al., “Asynchronous design using commercial HDL synthesis tools,” In Proc. Int. Symp. Asynchronous Circuits and Systems, 2000, pp. 114-125.
Martin, A. J., “The limitations to delay-insensitivity in asynchronous circuits,” Technical Report Caltech-CS-TR-90-02, Department of Computer Science, California Institute of Technology, 1990.
Martin, A., “Compiling communicating processes into delay-insensitive VLSI circuits,” Distributed Computing, 1986, 1(4).
Martin, A.J., “Asynchronous Datapaths and the Design of an Asynchronous Adder,” Formal Methods in System Design, 1: 117-137 (1992).
McCardle J. et al., “Measuring an asynchronous processor's power and noise,” In Proc. Synopsys User Group Conference, 2001.
Muller, D.E., “Asynchronous Logics and Application to Information Processing,” Switching Theory in Space Technology, Stanford University Press, 1963, pp. 289-297.
Nielsen, C.D., “Evaluation of Function Blocks for Asynchronous Design,” In Proc. EuroDAC'94, 1994, pp. 454-459.
Rotem, S. et al., “RAPPID: An Asynchronous Instruction Length Decoder,” In Proc. ASYNC'99, 1999, pp. 1-11.
Rudell, R.L. et al., “Multiple-Valued Minimization for PLA Optimization,” IEEE Transactions on Computer-Aided Design, vol. CAD-6, No. 5, Sep. 1987, pp. 727-750.
Rudell, R.L., “Logic Synthesis for VLSI Design,” Ph.D. thesis, UCB/ERL M89/49, Electronics Research Laboratory, University of California at Berkeley, 1989.
Singh, M. et al., “An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz,” In Proceeding of the Eighth International Symposium on Asynchronous Circuits and Systems (ASYNC '02), 2002, pp. 1-12.
Singh, N. P., “A design methodology for self-timed systems,” Technical Report MIT/LCS/TR-258, Laboratory for Computer Science, MIT, 1981, Master's thesis.
Smith, S. C. et al., “Optimization of NULL convention self-timed circuits,” Integration, the VLSI Journal, 2004, 37:135-165.
Smith, S.C. et al., “Delay-Insensitive Gate-Level Pipelining,” Intergration, The VLSI Journal, vol. 30, No. 2, Nov. 2001, pp. 103-131.
Sobelman, G. E. et al., “CMOS circuit design of threshold gate with hystersis,” In Proc. Int. Symp. Circuits Systems, 1998, pp. 61-64.
Spars, J. et al., “Design of delay insensitive circuits using multi-ring structures,” In Proc. European Des. Autom. Conf., 1992, pp. 15-20.
Van Berkel, C. H. et al., “Scanning the technology: Applications of asynchronous circuits,” Proc. IEEE, 1999, 87(2):223-233.
Van Berkel, K. et al., “Stretching quasi delay insensitivity by means of extended isochronic forks,” In Proc. Int. Symp. Asynchronous Circuits and Systems, 1995, pp. 99-106.
Van Berkel, K. et al., “VLSI programming of asynchronous circuits for low power,” Asynchronous Digital Circuit Design, 1995, pp. 151-210.
van Gageldonk, H. et al., “An Asynchronous Low-Power 80C51 Microcontroller,” In Proc. ASYNC '98, 1998, pp. 1-12.
Williams, T.E. et al., “A Zero-Overhead Self-Timed 160-ns 54-b CMOS Divider,” IEEE Journal of Solid-State Circuits. vol. 26, No. 11, Nov. 1991, pp. 1651-1661.
Zhou, Y. et al., “Cost-aware synthesis of asynchronous circuits based on partial acknowledgement,” In Proc. IEEE/ACM Int. Conf Computer-Aided Design, 2006.

Affiliated with

Also associated with

Rating

Methods, media, and means for forming asynchronous logic... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods, media, and means for forming asynchronous logic..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods, media, and means for forming asynchronous logic... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4169361