Methods for trench isolation with reduced step height

Details Methods for trench isolation with reduced step height Methods for trench isolation with reduced step height

2002-03-25

2003-05-27

Fahmy, Jr., Wael (Department: 2812)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S692000, C438S756000

Reexamination Certificate

active

06569747

ABSTRACT:

FIELD OF INVENTION
The present invention relates generally to semiconductor device fabrication and more particularly to improved trench isolation techniques for manufacturing semiconductor devices.
BACKGROUND OF THE INVENTION
Integrated circuits are fabricated by forming electrical devices on or in a semiconductor substrate and interconnecting these devices to form electrical circuits. In the design and manufacture of such semiconductor devices, it is necessary to isolate the individual electrical devices from one another, for example, to avoid parasitic transistor operation in adjacent MOSFET devices. Thusfar, a variety of techniques have been developed for electrically isolating devices in integrated circuit fabrication. One such technique is known as local oxidation of silicon (LOCOS), which involves selectively growing oxide in non-active or field regions of a substrate using a nitride mask overlying active regions thereof. However, as device geometries have been reduced beyond submicron sizes, conventional LOCOS isolation technologies have become ineffective, due to bird's beak and other shortcomings. Accordingly alternate isolation processes for CMOS and bipolar technologies have been developed for semiconductor devices such as logic and/or memory. One such technique includes shallow trench isolation (STI), in which isolated trenches are provided vertically into the substrate, which are then filled with electrically isolating materials such as silicon dioxide (SiO
2
). The resulting (e.g., filled trench) isolation structures separate and provide electrical isolation between electric devices such as transistors and/or memory cells subsequently formed on either side of the trench.
Electrical devices, such as transistors and memory cells are formed in a series of process steps, including the patterning process steps by which circuit patterns are transferred onto the surface layers of semiconductor wafers. Of particular importance is the patterning of polysilicon structures used to form gate contacts in transistor devices, where the gate dimensions are largely determinative of channel length and associated device performance characteristics. In this regard, it is known that patterning accuracy is facilitated by surface flatness. Accordingly it is desirable to provide a smooth, substantially planar surface while patterning a semiconductor wafer, particularly for small dimension patterning in high density devices. Lithographic techniques are employed in patterning semiconductor devices, which involve optically projecting patterns onto the wafer's surface. However, where the surface is not flat, the projected image will be distorted, causing undesirable effects including variance in critical device dimensions, such as transistor channel length corresponding to gate contact dimensions.
Referring to
FIGS. 1A-1G
, conventional STI processing of a semiconductor wafer
2
is illustrated, beginning in
FIG. 1A
with a thermal oxidation process to grow a barrier or pad oxide layer
4
(e.g., approximately 200-400 Å thick) over a semiconductor substrate
6
. A nitride layer
8
(e.g., Si
3
N
4
) is then deposited in
FIG. 1B
, such as by low pressure chemical vapor deposition (LPCVD). The nitride layer
8
is used to protect the active regions of the substrate
6
from adverse effects of the subsequent formation of isolation trenches between the active regions. In addition, the nitride layer thickness is increased to allow process control margin for non-self-stopping planarization following trench fill. Thus, the conventional nitride layer
8
is deposited to a thickness of about 2,000 Å, and can include arc layers such as SiN and SiRN. The active regions of the device
2
are then masked in
FIG. 1C
using a patterned etch mask
10
, leaving the isolation region of the nitride layer
8
exposed.
Thereafter an etch process
12
is employed to etch through the nitride layer
8
, the pad oxide
4
, and into the substrate
6
to form a trench
14
in the exposed isolation region. As illustrated in
FIG. 1D
, the active mask
10
is removed and a liner
16
is formed in the trench
14
, such as through thermal oxidation of the exposed portions of the trench
14
, in order to remove damage from the silicon etch process
12
. SiO
2
or other fill material
18
is then deposited in
FIG. 1E
to fill the trench
14
and also to cover the active substrate regions, which is done using a deposition process
20
. A wafer surface planarization process
22
is thereafter performed in
FIG. 1F
, typically through chemical mechanical polishing (CMP). Following planarization, the remainder of the nitride layer
8
is then stripped or removed using an etch process
24
in
FIG. 1G
, leaving a step having a height
26
generally equal to the post-CMP thickness of the removed nitride layer
8
. The step height
26
causes inaccuracies in subsequent gate contact formation in the active regions adjacent the trench
14
, resulting in variance in the critical gate dimensions.
The CMP processing
22
is a surface planarization operation involving rotation of the silicon wafer
2
against a polishing pad in the presence of an abrasive slurry (not shown) while applying pressure. The polishing pad, generally a polyurethane-based material, includes polymeric foam cell walls, which aid in removal of the reaction products at the wafer interface. The controlled pressure forces the abrasive particles of the slurry into intimate contact with the wafer surface, whereas the velocity of rotation controls mechanical removal rate as the abrasive slurry particles are transported to the wafer surface. However, the conventional CMP
22
is not a self-stopping process. Accordingly, the nitride layer
8
is typically made thicker to allow process margin to prevent the CMP processing
22
from damaging the underlying substrate. Once CMP planarization
22
is completed, the nitride layer
8
is removed and the underlying barrier or pad oxide layer
4
is regrown or reformed to provide a gate oxide layer of predetermined thickness in the active regions. Thereafter, the electrical devices, such as transistors and/or memory cells (not shown) are formed in or on the substrate, and dielectric and connection (metal) layers are processed to interconnect the devices.
During formation of such electrical devices, photo lithographic techniques are used to pattern various features to create structures thereof. For example, etch masks are patterned to define the length of polysilicon gate structures which are etched from a polysilicon layer deposited over the gate oxide layer. However, such photolithography processes are less accurate in the presence of non-planar surface features. One such non-planar surface characteristic is the step resulting from the removal of the nitride layer
8
following CMP planarization
22
. In the conventional STI processing described above, the step height
26
of the trench fill material
18
, which is the maximum field thickness above the active surface, is largely determined by the thickness of the nitride layer
8
after termination of the CMP polishing
22
. However, as noted above, the CMP process
22
is not controllable to a high degree of accuracy, and therefore, the post-CMP nitride layer thickness (and hence the step height
26
) may vary greatly. As a result, the corresponding misalignment inaccuracies in the subsequent poly gate patterning are variable as well, leading to undesirable variances in the critical dimensions (CDs) of subsequently formed electrical devices. Thus, there remains a need for improved techniques for isolating electrical devices in semiconductor devices by which these and other critical dimensions may be better controlled by reducing STI related step heights.
SUMMARY OF THE INVENTION
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention no

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