Methods for thermal management of three-dimensional...

Data processing: generic control systems or specific application – Specific application – apparatus or process – Specific application of temperature responsive control system

Reexamination Certificate

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Reexamination Certificate

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07487012

ABSTRACT:
A method of dynamic thermal management in a multi-dimensional integrated circuit or device is provided. The method includes monitoring on-chip temperatures, power dissipation, and performance of device layers. The method includes comparing on-chip temperatures to thermal thresholds, on-chip power dissipation to power thresholds and on-chip performance to performance thresholds. Also, the method includes analyzing interactions between temperatures, power, and performance of different device layers within the multi-dimensional integrated circuits. The method includes activating layer-specific thermal and power management within performance constraints on one or more device layers through actuators in the corresponding device layers, depending on the severity of heating.

REFERENCES:
patent: 5502838 (1996-03-01), Kikinis et al.
patent: 7050959 (2006-05-01), Pollard, II et al.
patent: 7091604 (2006-08-01), Wylie et al.
patent: 2001/0033030 (2001-10-01), Leedy
patent: 2007/0244676 (2007-10-01), Shang et al.
Mondal et al. “Thermally Robust Clocking Schemes for 3D Integrated Circuits” in Design, Automation & Test in Europe Conference & Exhibition, Apr. 2007 pp. 1-6.
David Brooks, et al.; “Dynamic Thermal Management for High-Performance Microprocessors”; International Symposium on High-Performance Computer Architecture; Jan. 2001.
“Power Management”; Wikipedia.org—Wikipedia Encyclopedia; Mar. 13, 2007.
Multi-core (computing); Wikipedia.org—Wikipedia Encyclopedia, Mar. 13, 2007.
A.W. Topol, et al., “Three-Dimensional Integrated Circuits”, IBM Journal of Research and Development, vol. 50, No. 4/5, pp. 491, 506; 2006.
Yuan Xie, et al. “Design Space Exploration for #D Architectures” AMC Journal on Emerging Technologies in Computing Systems, vol. 2, No. 2, Apr. 2006, pp. 65-103.
Bryan Black, et al. “Die Stacking (3D) Microarchitecture”, in Proceedings of The 39th Annual IEEE / ACM International SYmposium on Microarchitecture, Dec. 9-13, 2006, Orlando, Florida, USA.
J. Burns, et al., “Three-Dimensional Integration Circuits for Low-Power, High-Bandwidth Systems on a Chip” IEEE International Solid-State Circuits Conference, Feb. 2001.
Kaustav Banerjee, et al. 3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and System-on-Chip Integration, May 2001.
Jiang, H., et al.; “Benefits and Costs of Power-Gating Technique”, ICCD Proceedings of the 2005 International Conference on Computer Design; pp. 559-566; Year of Publication 2005; IEEE Computer Society Washington DC USA; retrieved via internet: http://portal.acm.org/citation.cfm?id=1097113.1097595 on Aug. 19, 2008.

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