Methods for testing and burn-in of integrated circuit chips

Details Methods for testing and burn-in of integrated circuit chips Methods for testing and burn-in of integrated circuit chips

1992-02-21

1992-09-22

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 51, 437209, H01L 2166

Patent

active

051496623

ABSTRACT:
Packaging methods and configurations are disclosed for placing electronic integrated circuit chips into operable chip systems in a manner to facilitate burn-in and testability thereof. The invention addresses the problem of testing bare integrated circuit chips before they are committed to a multichip module. Further, it addresses the problem of burning-in bare chips under biased conditions so that chips with defects therein can be accelerated to failure, thereby avoiding their incorporation into a multichip integrated circuit module. Pursuant to the invention, special connection arrays are disposed in spacer blocks in a predetermined configuation on a substrate. The blocks define areas of the substrate which preferably accommodate a plurality of integrated circuit chips such that each chip is surrounded on each side by a spacer block. One or more connection arrays may be provided in each spacer block. The connection arrays have interconnection pads which in the final structure are accessible to an external probing device. Specific methods of fabrication are also disclosed.

REFERENCES:
patent: 4937203 (1990-06-01), Eichelberger et al.
patent: 4953001 (1990-09-01), Kaiser, Jr. et al.
patent: 4962415 (1990-10-01), Yamamoto et al.
patent: 4981817 (1991-01-01), Stowe, Jr.
patent: 4985753 (1991-01-01), Fujioka et al.
patent: 5047711 (1991-09-01), Smith et al.

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