Methods for simultaneous analog-to-digital conversion and...

Details Methods for simultaneous analog-to-digital conversion and... Methods for simultaneous analog-to-digital conversion and...

1999-03-22

2002-03-26

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S169000, C348S571000

Reexamination Certificate

active

06362767

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to analog-to-digital conversion methods and to methods of performing electronic multiplication. More specifically, the present invention provides a method of performing analog-to-digital conversion simultaneously with multiplication. The invention is particularly well suited for use in data compression of a large number of parallel analog signals. In addition, the present disclosure teaches an architecture for performing a separable transform on a 2-dimensional imaging sensor array.
BACKGROUND OF THE INVENTION
Imaging sensor arrays such as charge coupled devices (CCDs) or photodiode arrays are commonly used in imaging applications such as machine vision or digital cameras. Such imaging arrays typically comprise 500,000 to 1,000,000 microscopic light sensors arranged on the surface of the imaging chip. Each sensor generates an analog value (e.g., voltage) which is a function of the incident light intensity. For an image to be stored, it is generally necessary to digitize the analog value from each sensor.
Digitization is typically performed with a high speed analog-to-digital converter (ADC) which sequentially digitizes the analog signal from each sensor. The large number of sensors in an imaging array results in a large amount of data being produced by each image acquired. Therefore, for most imaging devices, some kind of data compression scheme is employed to make the digitized image easier to store and transmit.
Separable 2-D transforms are commonly used for data compression because they are relatively easy to implement (because they are ‘separable’). JPEG and MPEG are examples of image data compression techniques that use separable 2-D transforms.
FIG. 1
shows an 8×8 pixel array and illustrates some of the basic concepts involved in a separable 2-D transform. In a separable 2-D transform, the digital values from each row and each column are multiplied by a precomputed digital coefficient (R
1
, R
2
, . . . R
8
; C
1
, C
2
, . . . C
8
). In this way, each pixel value is multiplied by a number R
i
C
j
, where i and j are integers between 1 and 8. The computation and use of separable 2-D transforms is well known in the art of signal processing. There exist many different kinds of separable 2-D transforms. Many data compression techniques, including separable 2-D transforms, require a large number of arithmetic multiplications to be performed, due to the large number of digitized pixel values. It is noted that the 8×8 pixel array of
FIG. 1
is typically only a small block in a larger pixel array having many thousands of pixels.
The current approach to performing these multiplications (for example, in a digital camera) is to output the digital pixel values to a dedicated digital signal processor to perform the digital multiplications. This can be a problem because it requires a relatively expensive processing chip and consumes a lot of power.
An alternative approach suggested in the literature performs multiplication directly on the analog values before digitization, followed by variable step size quantization (digitization). This approach is undesirable because it requires analog memory and sophisticated analog processing which requires large silicon area and power and can be complex to implement. For more information, reference can be made to “
A Compressed Digital Output CMOS Image Sensor with Analog
2-D
Discrete Cosine Transform Processors and ADC/Quantizer
”, by S. Kawahito et al. ISSCC Digest of Technical Papers, San Francisco, Calif., February 1997.
U.S. Pat. No. 5,801,657 to Fowler et al. discloses a method and apparatus for performing analog-to-digital conversion (ADC) at the pixel level. In other words, each pixel is provided with a simple ADC. Each ADC receives inquiry signals from a driving circuit outside the sensor array. Only one driving circuit is needed for the entire array. The digital pixel values are outputted serially. The method is called Multi-Channel Bit Serial (MCBS) Analog-to-digital Conversion. A single channel version of MCBS is termed a Bit Serial ADC. An MCBS ADC has many advantages applicable to image acquisition, but it does not provide digital multiplication. If a separable 2-D transform is to be performed on an MCBS-digitized image, an additional digital signal processor is required. This increases the cost and power consumption of an imaging device.
Therefore, it would be desirable to be able to perform multiplication on a series of digitized values without needing a separate digital signal processor.
Also, since MCBS ADCs have many advantages, it would be desirable to perform multiplication using the MCBS hardware and method previously disclosed.
SUMMARY OF MCBS ADC OPERATION
(Prior Art)
FIG. 2
shows a single channel bit serial ADC according to U.S. Pat. No. 5,801,657 to Fowler et al.
A single channel bit serial ADC comprises a comparator
20
and a one-bit latch
22
. An output
32
of the comparator is connected to the latch gate input
34
. A monotonicaly increasing stairstep RAMP signal
24
enters a comparator inverting input
30
and an analog value (a voltage)
28
to be digitized enters a comparator noninverting input
26
. Therefore, when the RAMP
24
exceeds the analog voltage
28
, output
32
of the comparator goes low. The comparator output enters a gate
34
of the latch
22
. BITX
36
enters data input
38
of latch
22
. Therefore, when the RAMP signal exceeds the analog voltage
28
, the latch
22
latches the BITX value. The latched BITX value is provided at the serial digital output.
FIG. 3
is a diagram illustrating the interaction between RAMP and BITX signals. RAMP
24
is a staircase waveform with predetermined voltage levels
40
and voltage steps
46
. BITX is a squarewave. BITX has transitions
42
that are timed so that there is a delay
44
between the BITX transition
42
and RAMP voltage steps
46
. The delay
44
provides the latch with a set-up time before the comparator changes states.
RAMP and BITX are designed together such that desired digital values (0 or 1) are associated with predetermined analog voltage ranges, shown as A-B, B-C, C-D, D-E, and E-F. The voltage ranges are determined by the voltage steps
46
of the RAMP signal.
FIG. 4
shows a quantization table for the RAMP and BITX signals of FIG.
3
. The digital output associated with the voltage ranges is changed by changing BITX.
The bit serial ADC technique can be used to digitize analog values to multiple bits of precision. The bits are output serially. The bits can be output in any order desired: the most significant bit (MSB) can come first, or the least significant bit (LSB) can come first, for example. A distinct RAMP waveform is required for each bit of precision. The data is output from the latch output between each RAMP waveform. The voltage levels
40
of RAMP and the pattern of BITX can be changed to output any desired quantization table. For example, gray code can be output by appropriately designing BITX and RAMP.
One of the great advantages of bit serial ADCs is that many separate ADCs can be operated in parallel to form a Multi-Channel Bit Serial (MCBS) ADC. This is shown in FIG.
5
. The circuitry that generates RAMP and BITX delivers the same RAMP and BITX to all the ADCs
48
. Since the hardware for each ADC is so simple, many ADCs (e.g., thousands) can operate in parallel. This feature makes the MCBS ADC particularly useful in applications where a large number of analog values must be digitized. This situation arises, for example, in the digitization of analog signals from an image sensor. In an image sensor, a single ADC can be provided for each pixel, or small group of pixels.
OBJECTS AND ADVANTAGES OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide a method of performing digital multiplication that:
1) is fully compatible with the Multi-Channel Bit Serial analog-to-digital conversion method and hardware,
2) requires no additional hardware to be added to the existing MCBS circuitry,
3) can be used to multiply each d

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