Methods for repairing defects on a semiconductor substrate

Details Methods for repairing defects on a semiconductor substrate Methods for repairing defects on a semiconductor substrate

2000-03-24

2003-06-24

Nguyen, Nam (Department: 1741)

Electrolysis: processes, compositions used therein, and methods

Electrolytic coating

Repairing

C205S123000, C205S206000, C205S087000, C156S345120, C438S633000, C438S690000, C438S759000

Reexamination Certificate

active

06582579

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to methods for repairing defects on a semiconductor substrate. More particularly, the present invention is directed to methods for repairing defects on a top surface of the substrate by selectively plating over the defective portions while preventing deposition in the non-defective portions. In addition, the present invention relates to planarizing a non-planar conductive surface of a substrate.
BACKGROUND OF THE INVENTION
Depositing a conductive material such as metal in damascene type cavities (i.e., trenches, holes, and vias) of a semiconductor substrate (i.e., wiring structure) is an important and necessary process in fabricating integrated chips and devices. The conductive material is deposited in the cavities of the substrate to interconnect layers and components contained therein. Recently, there is great interest in using copper as the conductive material as it provides better conductivity and reliability than, for example, aluminum or aluminum alloys.
FIG. 1A
illustrates a cross sectional view and
FIG. 1B
illustrates a perspective view of a substrate after depositing the conductive material in the cavities. These figures illustrate a dielectric or insulating layer
2
(e.g., silicon dioxide—SiO
2
) having deposited thereon an adhesive or barrier layer
4
. The insulating layer
2
is generally etched to form the cavities
12
therein before the barrier layer
4
is deposited thereon. The cavities
12
in the insulating layer
2
are generally etched using a reactive ion etching (RIE) method. The barrier layer
4
is generally deposited on the insulating layer
2
using any of the various sputtering methods, chemical vapor deposition (CVD), electro-deposition or electroless plating method. The barrier layer
4
may be tantalum (Ta), titanium (Ti), tungsten (W), titanium-tungsten (TiW), titanium nitride (TiN), Nb, CuWP, CoWP, or other materials or combinations thereof that are commonly used in this field.
After the barrier layer
4
is deposited on the insulating layer
2
, a seed layer (not shown) is generally deposited thereon before the conductive material
6
such as copper is deposited on the substrate. In general, the seed layer is the same material as the conductive material
6
. The conductive material
6
can be deposited using CVD, sputtering, electroless plating, electro-deposition, or combinations thereof.
The depths of the cavities
12
in the insulating layer
2
can range from 0.02 to 200 um for interconnects and up to 1000 um or more for packages. The conductive material
6
is generally deposited over the entire top surface of the substrate, i.e. in the cavities
12
as well as on the field regions
3
. It should be noted that the field regions
3
are defined as the top surface area of the substrate between the cavities
12
. The excess material deposited over the top plane of the field regions
3
is known as the overburden. The thickness of the overburden may change over the various features of the substrate depending on their size. For example, in general, the overburden is thicker over the smaller cavities than the larger cavities.
Once the conductive material
6
is formed in the cavities
12
and on the field regions
3
, the substrate is typically transferred to an apparatus for polishing and removing the overburden from the top surface (i.e., field regions). Typically, the substrate is polished using a conventional chemical mechanical polishing (CMP) device and abrasive slurry. While using this method, some conductive material
6
grains may be removed from the cavities
12
, thereby resulting in substrates with various defects. For example, certain grains of the conductive material
6
in the cavities
12
may be corroded away because the abrasive slurry may attach itself to the conductive material
6
grains. Thus, some grains of the conductive material
6
may be etched away from the cavities
12
, leaving defective portions
8
. Alternatively, defective portions
8
may result from deep scratches during the CMP process.
Defective portions
8
may also result from the conductive material
6
deposition process itself. For example, non-optimal deposition processes may give rise to voids in conductive material
6
, and after polishing, such voids may result in the defective portions
8
. Further, residual conductive material
10
may not be completely removed and left on the barrier layer
4
, thereby resulting in additional defects. As known, defects typically reduce the quality of the conductive material
6
and device performance.
FIG. 2
illustrates a cross sectional view of a substrate having dishing effects. During the CMP process, “dishing” or non-planar polishing may result because of over polishing. A large recess
14
may be formed in a large test pad portion, while a small recess
16
may be formed in a small bus line portion on the cavities
12
of the substrate. In addition, when the substrate is exposed to the abrasives during the CMP process, corrosion and other undesirable characteristics may result (i.e., dishing). Dishing may also result from wet etching processes. It is well known that existence of any kind of defects in the deposited conductive material results in poor device performance and low process yield.
Accordingly, there is a need for methods for repairing defects on semiconductor substrates.
SUMMARY OF THE INVENTION
In view of the above-described problems of the prior art, it is an object of the present invention to provide a method for repairing defects on a semiconductor substrate.
It is another object of the present invention to provide a method for repairing defects on a semiconductor substrate by selectively plating over the defective portions while preventing or minimizing deposition on the non-defective portions.
It is another object of the present invention to provide a method for depositing a conductive material in defective portions of the cavities on the substrate.
It is a further object of the present invention to provide a method for providing a uniform conductive material overburden on the substrate without depositing the conductive material on the field regions of the substrate.
It is yet another object of the present invention to provide a method for depositing a second conductive material on the first conductive material of a substrate.
It is yet another object of the present invention to provide a method that minimizes the disparity of the conductive material overburden across a substrate while repairing defects on the substrate.
These and other objects are achieved by providing methods for repairing defects on the substrate in an efficient and reliable manner. The present invention relates to methods for repairing defects on a semiconductor substrate. This is accomplished by selectively depositing the conductive material in defective portions in the cavities while removing residual portions from the field regions of the substrate. Another method according to the present invention includes forming a uniform conductive material overburden on the top surface of the substrate. The present invention also discloses a method for depositing a second conductive material on the first conductive material of the substrate.


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