Methods for reduced trench isolation step height

Details Methods for reduced trench isolation step height Methods for reduced trench isolation step height

2002-03-25

2003-09-02

Cuneo, Kamand (Department: 2829)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S296000, C438S437000, C438S633000, C438S689000

Reexamination Certificate

active

06613646

ABSTRACT:

FIELD OF INVENTION
The present invention relates generally to semiconductor device fabrication and more particularly to improved trench isolation techniques for reducing step heights in the manufacture of semiconductor devices.
BACKGROUND OF THE INVENTION
Integrated circuits are fabricated by forming electrical devices on or in a semiconductor substrate and interconnecting these devices to form electrical circuits. In the design and manufacture of such semiconductor devices, it is necessary to isolate the individual electrical devices from one another, for example, to avoid parasitic transistor operation in adjacent MOSFET devices. Thusfar, a variety of techniques have been developed for electrically isolating devices in integrated circuit fabrication. One such technique is known as local oxidation of silicon (LOCOS), which involves selectively growing oxide in non-active or field regions of a substrate using a nitride mask overlying active regions thereof. However, as device geometries have been reduced beyond submicron sizes, conventional LOCOS isolation technologies have become ineffective, due to bird's beak and other shortcomings. Accordingly alternate isolation processes for CMOS and bipolar technologies have been developed for semiconductor devices such as logic and/or memory. One such technique includes shallow trench isolation (STI), in which isolation trenches are provided vertically into the substrate, which are then filled with electrically isolating materials such as silicon dioxide (SiO
2
). The resulting (e.g., filled trench) isolation structures separate and provide electrical isolation between electric devices such as transistors and/or memory cells subsequently formed on either side of the trench.
Electrical devices, such as transistors and memory cells are formed in a series of process steps, including the patterning process steps by which circuit patterns are transferred onto the surface layers of semiconductor wafers. Of particular importance is the patterning of polysilicon structures used to form gate contacts in transistor devices, where the gate dimensions are largely determinative of channel length and associated device performance characteristics. In this regard, it is known that patterning accuracy is facilitated by surface flatness. Accordingly it is desirable to provide a smooth, substantially planar surface while patterning a semiconductor wafer, particularly for small dimension patterning in high density devices. Lithographic techniques are employed in patterning semiconductor devices, which involve optically projecting patterns onto the wafer's surface. However, where the surface is not flat, the projected image will be distorted, causing undesirable effects including variance in critical device dimensions, such as transistor channel length corresponding to gate contact dimensions.
Referring to
FIGS. 1A-1G
, conventional STI processing of a semiconductor wafer
2
is illustrated, beginning in
FIG. 1A
with a thermal oxidation process to grow a barrier or pad oxide layer
4
having a thickness
4
′ of about 200-400 Å over a semiconductor substrate
6
. A nitride layer
8
(e.g., Si
3
N
4
) is then deposited in
FIG. 1B
, such as by low pressure chemical vapor deposition (LPCVD). The nitride layer
8
is used to protect the active regions of the substrate
6
from adverse effects of the subsequent formation of isolation trenches between the active regions. In addition, the nitride layer thickness is set so as to allow process control margin for non-self-stopping planarization following trench fill. Thus, the conventional nitride layer
8
is deposited to a thickness
8
′ of about 2,000 Å. The active regions of the device
2
are then masked in
FIG. 1C
using a patterned etch mask
10
, leaving the isolation region of the nitride layer
8
exposed.
Thereafter an etch process
12
is employed to etch through the nitride layer
8
, the barrier oxide
4
, and into the substrate
6
to form a trench
14
in the exposed isolation region. As illustrated in
FIG. 1D
, the active mask
10
is removed and a liner
16
is formed in the trench
14
, such as through thermal oxidation of the exposed portions of the trench
14
, in order to remove damage from the silicon etch process
12
. SiO
2
or other fill material
18
is then deposited in
FIG. 1E
via a deposition process
20
to fill the trench
14
and also to cover the nitride layer
8
in the active substrate regions. A chemical mechanical polishing (CMP) process
22
is then employed in
FIG. 1F
, to planarize the wafer surface, which exposes the upper surface of the nitride layer
8
. Following planarization, the nitride layer
8
is then removed via an etch process
24
in
FIG. 1G
, leaving a step between the barrier oxide
4
and the top of the remaining trench fill material
18
having a step height
26
generally equal to the post-CMP thickness
8
′ of the removed nitride layer
8
. In
FIGS. 1F and 1G
, a somewhat ideal case is illustrated, wherein the conventional CMP process
22
is stopped once the nitride layer
8
is exposed. In such a situation, the pre and post-CMP nitride layer heights
8
′ are essentially equal (e.g., FIGS.
1
B and
1
F). However, referring to
FIGS. 1H and 1I
, conventional CMP processing, such as using polyurethane polishing pads and abrasive slurries, are not self-stopping processes, and thus the post-CMP height
8
″ (
FIG. 1H
) is seldom equal to the pre-CMP nitride thickness
8
′ (FIG.
1
B). In
FIG. 1H
, for example, the CMP process
22
removes the oxide material
18
over the nitride layer
8
, and continues thereafter, removing an upper portion of the nitride layer
8
(e.g., over-polishing). Thus, the illustrated post-CMP nitride layer thickness
8
″ is much different than the initial thickness
8
′ of FIG.
1
B.
As can be seen in
FIG. 11
, the over-polishing associated with the CMP process
22
results in a step height
26
′ much lower than the step height
26
in FIG.
1
G. The existence of the step heights
26
,
26
′ in
FIGS. 1G and 1I
has been found to cause inaccuracies in subsequent gate contact formation in the active regions adjacent the trench
14
, resulting in variance in the critical gate dimensions. The variance in such step heights, due to the non-self-stopping nature of conventional CMP planarization techniques, further hinders efforts at controlling such critical dimensions. For instance, the step heights
26
,
26
′ have been found to vary from about 300 to about 2000 Å. Consequently, it is difficult to control the step heights
26
,
26
′ where conventional CMP planarization processes are employed.
The conventional CMP processing
22
typically involves rotation of the silicon wafer
2
against a polishing pad in the presence of an abrasive slurry (not shown) while applying pressure. The polishing pad, generally a polyurethane-based material, includes polymeric foam cell walls, which aid in removal of the reaction products at the wafer interface. The controlled pressure forces the abrasive particles of the slurry into intimate contact with the wafer surface, whereas the velocity of rotation controls mechanical removal rate as the abrasive slurry particles are transported to the wafer surface. However, the conventional CMP
22
is not a self-stopping process. Accordingly, the nitride layer
8
is typically made thick, for example about 2000 Å, in order to allow process margin to prevent the CMP processing
22
from damaging the underlying substrate. Thus, the initial nitride layer thickness
8
′ is typically tailored to accommodate over-polishing associated with the conventional CMP process
22
. Following the CMP process
22
, the nitride layer
8
is removed and the underlying barrier or pad oxide layer
4
may be regrown or reformed to provide a gate oxide layer of predetermined thickness in the active regions. Thereafter, the electrical devices, such as transistors and/or memory cells (not shown) are formed in or on

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