Methods for providing void-free layers for semiconductor assembl

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Insulative housing or support

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438118, H01L 2144

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active

058343393

ABSTRACT:
A method for the removal of voids and gas bubbles within uncured or partially cured microelectronic component encapsulants and adhesive/chip attach layers. A sealed void or gas bubble within a gap between a microelectronic component and a supporting substrate is substantially eliminated through the application of a uniform pressure (isostatic or hydrostatic) and energy such that a substantially void/bubble free interposer layer is created.

REFERENCES:
patent: 5120678 (1992-06-01), Moore et al.
patent: 5148265 (1992-09-01), Khandros et al.
patent: 5148266 (1992-09-01), Khandros et al.
patent: 5194930 (1993-03-01), Papathomas et al.
patent: 5203076 (1993-04-01), Banerji et al.
patent: 5249101 (1993-09-01), Frey et al.
patent: 5288944 (1994-02-01), Bronson et al.
patent: 5289346 (1994-02-01), Carey et al.
patent: 5385869 (1995-01-01), Liu et al.

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