Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2008-04-15
2008-04-15
Tran, Michael T (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185240
Reexamination Certificate
active
11481022
ABSTRACT:
Methods for programming and reading a multi-level-cell NAND flash memory device having plural memory cells are disclosed to reduce the programming time and the reading time. The program method comprises the steps of: (a) programming the zero state memory cells, the first state memory cells, the second state memory cells and the third state memory cells to a zero state, (b) programming the second state memory cells from the zero state to a second state by switching the MSBs of the second state memory cells, and (c) programming the first state memory cells from the zero state to a first state by switching the LSBs of the first state memory cells and simultaneously programming the third state memory cells from the second state to a third state by switching the LSBs of the third state memory cells. The read method comprises the steps of: (d) reading the MSBs of the zero state memory cells, the first state memory cells, the second state memory cells, and the third state memory cells by a first verify signal and a second verify signal, and (e) reading the LSBs of the zero state memory cells, the first state memory cells, the second state memory cells, and the third state memory cells by the first verify signal and a third verify signal. A page buffer is also disclosed to perform the methods for programming and reading a multi-level-cell NAND flash memory device.
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Chen Chung Zen
Wang Jo Yu
Wu Fu An
Elite Semiconductor Memory Technology Inc
Oliff & Berridg,e PLC
Tran Michael T
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