Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Patent
1993-08-20
1995-10-03
Mintel, William
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
257693, 257793, 437208, 437227, H01L 2310, H01L 2331, H01L 23485
Patent
active
054554551
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to methods and apparatus for producing integrated circuit devices and to integrated circuit devices produced thereby.
BACKGROUND OF THE INVENTION
An essential step in the manufacture of all integrated circuit devices is known as "packaging" and involves mechanical and environmental protection of a silicon chip which is at the heart of the integrated circuit as well as electrical interconnection between predetermined locations on the silicon chip and external electrical terminals.
At present three principal technologies are employed for packaging semiconductors: Wire bonding, tape automatic bonding (TAB) and flip chip.
Wire bonding employs heat and ultrasonic energy to weld gold bonding wires between bond pads on the chip and contacts on the package.
Tape automatic bonding (TAB) employs a copper foil tape instead of bonding wire. The copper foil tape is configured for each specific die and package combination and includes a pattern of copper traces suited thereto. The individual leads may be connected individually or as a group to the various bond pads on the chip.
Flip chips are integrated circuit dies which have solder bumps formed on top of the bonding pads, thus allowing the die to be "flipped" circuit side down and directly soldered to a substrate. Wire bonds are not required and considerable savings in package spacing may be realized.
The above-described technologies each have certain limitations. Both wire bonding and TAB bonding are prone to bad bond formation and subject the die to relatively high temperatures and mechanical pressures. Both wire bond and TAB technologies are problematic from a package size viewpoint, producing integrated circuit devices having a die-to-package area ratio ranging from about 10% to 60%.
The flip-chip does not provide packaging but rather only interconnection. The interconnection encounters problems of uniformity in the solder bumps as well as in thermal expansion mismatching, which limits the use of available substrates to silicon or materials which have thermal expansion characteristics similar to those of silicon.
SUMMARY OF THE INVENTION
The present invention seeks to provide apparatus and techniques for production of integrated circuit devices which overcome many of the above limitations and provide integrated circuits of relatively smaller size and weight and enhanced electrical performance.
There is thus provided in accordance with a preferred embodiment of the present invention a method for producing integrated circuit devices including the steps of:
producing a plurality of integrated circuits on a wafer having first and second planar surfaces, each of the integrated circuits including a multiplicity of pads;
waferwise attaching to both said surfaces of the wafer a layer of protective material; and
thereafter slicing the wafer and the protective material attached thereto, thereby to define a plurality of prepackaged integrated circuit devices.
It is noted that the term "waferwise" does not require that a whole wafer be so processed at a given time. "Waferwise" applies equally to steps applied to multiple dies prior to dicing thereof.
In accordance with a preferred embodiment of the present invention the step of slicing exposes sectional surfaces of the multiplicity of pads.
Preferably the step of slicing cuts pads so as to simultaneously define electrical contact regions for both of a pair of adjacent integrated circuits.
Additionally in accordance with a preferred embodiment of the present invention there is provided a method for producing integrated circuit devices including the steps of:
producing a plurality of integrated circuits on a wafer, each of the integrated circuits including a multiplicity of pads; and
thereafter slicing the wafer, thereby to define a plurality of integrated circuit elements, and wherein the step of slicing exposes sectional surfaces of the multiplicity of pads.
Preferably the step of slicing cuts a plurality of pads including some which communicate with a one of a pair
REFERENCES:
patent: 3644801 (1972-02-01), Sheldon
patent: 4294092 (1988-12-01), Solomon
patent: 4383886 (1917-05-01), Nakamura
patent: 4933898 (1990-06-01), Gilberg et al.
patent: 4962249 (1990-08-01), Carlson
patent: 4971930 (1990-11-01), Eusaroli
patent: 4984358 (1991-01-01), Nelson
patent: 5104820 (1992-04-01), Go
patent: 5126286 (1992-06-01), Chance
patent: 5147815 (1992-09-01), Casto
patent: 5185295 (1993-02-01), Goto
patent: 5266833 (1993-11-01), Capps
patent: 5292686 (1994-03-01), Kiley
D. Richmould, Micro SMT Integrated Circuit Techical White Paper, Micro SMT Inc. Jan. 25, 1993.
Brown Peter Toby
Mintel William
LandOfFree
Methods for producing packaged integrated circuit devices and pa does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods for producing packaged integrated circuit devices and pa, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods for producing packaged integrated circuit devices and pa will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1079223