Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – Groove
Patent
1997-04-14
1999-07-20
Prenty, Mark V.
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
Groove
257686, H01L 2906
Patent
active
059259248
ABSTRACT:
Integrated Circuit ("IC") chips are formed with precisely defined edges and sizing. At the wafer processing level, trenches are lithographically etched in the kerf regions to define the edges of the IC chips on the wafer. The trenches are filled with insulating material, and upper level wiring and metallization is completed for the IC chips on the wafer. Further trenches are defined down to the filled previously formed trenches. The wafer is thinned from its bottom up to the filled trenches, and the insulating material therein is removed to separate the individual IC chips from the wafer. The precision of IC chip edge definition facilitates forming the IC chips into stacks more easily because many stack level alignment processes become unnecessary.
REFERENCES:
patent: 4325182 (1982-04-01), Tefft et al.
patent: 4707218 (1987-11-01), Giammarco et al.
patent: 4822755 (1989-04-01), Hawkins et al.
patent: 4925808 (1990-05-01), Richardson
patent: 4990462 (1991-02-01), Sliwa, Jr.
patent: 5075253 (1991-12-01), Sliwa, Jr.
patent: 5104820 (1992-04-01), Go et al.
patent: 5107586 (1992-04-01), Eichelberger et al.
patent: 5122481 (1992-06-01), Nishiguchi
patent: 5162251 (1992-11-01), Poole et al.
patent: 5270261 (1993-12-01), Bertin et al.
patent: 5293061 (1994-03-01), Hosaka
patent: 5434094 (1995-07-01), Kobiki et al.
patent: 5478781 (1995-12-01), Bertin et al.
patent: 5480832 (1996-01-01), Miura et al.
patent: 5482887 (1996-01-01), Duinkerken et al.
patent: 5691248 (1997-11-01), Cronin et al.
Cronin John Edward
Howell Wayne John
Kalter Howard Leo
Marmillion Patricia Ellen
Palagonia Anthony
International Business Machines - Corporation
Prenty Mark V.
LandOfFree
Methods for precise definition of integrated circuit chip edges does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods for precise definition of integrated circuit chip edges, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods for precise definition of integrated circuit chip edges will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1324082