Methods for packaging integrated circuit devices including cavit

Details Methods for packaging integrated circuit devices including cavit Methods for packaging integrated circuit devices including cavit

1999-02-11

1999-12-14

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

438118, 438456, H01L 2182

Patent

active

060016736

ABSTRACT:
A method for packaging an integrated circuit device includes forming a dielectric support layer on the surface of a substrate wherein the dielectric support layer includes an opening therein exposing at least a portion of an active region of the substrate. A protective layer is provided on the dielectric support layer opposite the substrate wherein the protective layer covers the exposed portion of the active region of the substrate thereby defining a cavity between the protective layer and the active region. More particularly, the step of forming the dielectric support layer can include forming a continuous dielectric layer on the surface of the substrate including the active region, and removing portions of the continuous dielectric layer from the active region to provide the opening of the dielectric support layer. Related structures are also discussed.

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Crowley, Robert T, et al., Chip-Size Packaging Developments, TechSearch International, Inc. , pp. 101-109 (Aug. 1995).

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