Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
1999-09-14
2002-09-24
Talbott, David L. (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S124000, C438S127000, C029S827000, C029S841000, C029S855000
Reexamination Certificate
active
06455356
ABSTRACT:
SUMMARY OF THE INVENTION
The present invention is directed toward improved plastic packages for housing an integrated circuit die, and to leadframes and methods for making such packages. In one embodiment of an assembly method for a package within the present invention, Step 1 provides a metal leadframe. The leadframe includes a disposable rectangular frame. A die pad is within and connected to the frame. A plurality of leads extend laterally from the frame toward the die pad without contacting the die pad.
The die pad of the leadframe has a rectangular perimeter. The die pad has a horizontal first surface upon which a die is placed during package assembly. Opposite the first surface is a substantially planar central second surface and a peripheral substantially planar third surface. The third surface is at the periphery of the second surface, and is vertically recessed from the second surface, so that the lower surface of die pad has a stepped profile. In a completed package, encapsulant material fills in beneath the recessed third surface of the die pad, but does not cover the second surface of the die pad. The encapsulant material beneath the third surface of the die pad prevents the die pad from being pulled vertically from the package.
Each lead has a first surface, a second surface that is opposite the first surface, and a third surface that also is opposite the first surface and adjacent to the second surface. The second surface has a rectangular or circular perimeter. The third surface is vertically recessed from the second surface, which results in the lower surface of the lead having a stepped profile. In a completed package, encapsulant material fills in beneath the third surface of the lead, but does not cover the second surface of the lead. The second surface of the lead serves as a contact for connecting the package externally, as in an LCC package, or serves as a land for the connection of a solder ball. The encapsulant material beneath the third surface of the lead prevents the lead from being pulled vertically from the package.
The leadframe is formed by a two-step wet etching process from a rolled metal strip. The first etching step is a one or two sided etch that etches through the metal strip and thereby transfers the desired overall pattern of the leadframe into the metal strip. The second etching step is a single-sided etch that etches the periphery of the die pad and selected portions of the leads. The second step etches partially through the thickness of the die pad and leads, and thereby forms the above-described, vertically recessed, planar or substantially planar third surfaces in the die pad and the leads.
Step 2 places an integrated circuit on the upper first surface of the die pad. Depending on the application, the area of the die may be less than the area of the first surface of the die pad, or may be greater in area such that the die overhangs the peripheral sides of the die pad. In some cases, the die also overhangs part of the length of the leads.
Step 3 electrically connects a bond wire or an equivalent conductor between each bonding pad of the die and a first surface of each lead. The portion of the lead to which the bond wire is connected may be plated, for example, with silver, gold, or other metals.
Step 4 applies a viscous adhesive encapsulant material onto the die and the upward facing first surface of the leadframe. The encapsulant material is then hardened. The encapsulant material covers the die, the bond wires, the first surfaces of the leads, the third surfaces of the die pad and leads, and the side surfaces of the die pad and leads. The second surfaces of the die pad and leads are not covered by encapsulant material, but rather are exposed at the lower external surface of the package.
Step 5 plates the exposed surfaces of the leadframe, including the exposed second surfaces of the die pad and leads, with a metal, such as copper, gold, lead-tin solder, tin, nickel, palladium, or any solderable metal. Depending on the application and the material used for making the leadframe, Step 5 may be omitted.
Step 6 severs a completed package from the encapsulated leadframe. In particular, step 6 obliterates the disposable portions of the leadframe and/or severs the disposable portions of the leadframe, such as the rectangular frame, from the non-disposable components of the leadframe, such as the die pad and leads. Depending on the method of encapsulation used in step 4, step 6 also may cut the encapsulant material to form peripheral sides of the package.
Step 6 severs the leads from the leadframe. The cut is made inside the dam bar. Depending on where the cut is made, an end portion of the severed lead may extend laterally beyond the sides of the package. Step 6 or a subsequent step also may include bending this protruding end portion of the severed lead up the side of the package so that the end portion of the lead is at an oblique angle to the lower external surface of the package and the encapsulated remainder of the lead. When the package is soldered to a printed circuit board, solder may be connected to the upwardly bent end portion of the severed lead in addition to the horizontal portion of the lead exposed at the lower external surface of the package to strengthen the solder connection. The lower external surface of the package includes: the second surface of the die pad, which is at the center of the bottom surface of the package; the second surfaces of the leads, and hardened encapsulant material, which forms the remainder of the bottom surface of the package and isolates the die pad and leads from each other.
The package of the present invention has numerous advantages, and is useful in numerous applications, including power devices and analog devices. The package may be made small in size. For example, the packages may be near chip size. In addition, the packages may be very thin. Packages having thickness as low as about 0.5 mm or less can be fabricated according the present invention. In addition, the leads can be placed close to the die, minimizing the length of bond wires. The exposed second surface of the die pad can be connected by metal solder to the printed circuit board for package cooling.
Numerous variations of the leadframe, package, and assembly method described above also are described in this application, and also form part of the present invention. For example, in one alternative assembly method, a leadframe is provided which allows a plurality of packages to be constructed simultaneously.
REFERENCES:
patent: 3838984 (1974-10-01), Crane et al.
patent: 4530152 (1985-07-01), Roche et al.
patent: 4707724 (1987-11-01), Suzuki et al.
patent: 4756080 (1988-07-01), Throp, Jr. et al.
patent: 4812896 (1989-03-01), Rothgery et al.
patent: 5041902 (1991-08-01), McShane
patent: 5157480 (1992-10-01), McShane et al.
patent: 5172213 (1992-12-01), Zimmerman
patent: 5172214 (1992-12-01), Castro
patent: 5200362 (1993-04-01), Lin et al.
patent: 5200809 (1993-04-01), Kwon
patent: 5214845 (1993-06-01), King et al.
patent: 5216278 (1993-06-01), Lin et al.
patent: 5221642 (1993-06-01), Burns
patent: 5258094 (1993-11-01), Furui et al.
patent: 5273938 (1993-12-01), Lin et al.
patent: 5277972 (1994-01-01), Sakumoto et al.
patent: 5278446 (1994-01-01), Nagaraj et al.
patent: 5279029 (1994-01-01), Burns
patent: 5332864 (1994-07-01), Liang et al.
patent: 5336931 (1994-08-01), Juskey et al.
patent: 5343076 (1994-08-01), Katayama et al.
patent: 5406124 (1995-04-01), Morita et al.
patent: 5424576 (1995-06-01), Djennas et al.
patent: 5435057 (1995-07-01), Bindra et al.
patent: 5474958 (1995-12-01), Djennas et al.
patent: 5521429 (1996-05-01), Aono et al.
patent: 5604376 (1997-02-01), Hamburgen et al.
patent: 5608267 (1997-03-01), Makulikar et al.
patent: 5639990 (1997-06-01), Nishihara et al.
patent: 5640047 (1997-06-01), Nakashima
patent: 5641997 (1997-06-01), Ohta et al.
patent: 5646831 (1997-07-01), Manteghi
patent: 5650663 (1997-07-01), Parthasarathi
patent: 5683806 (1997-11-01), Sakumoto et al.
patent: 5696666 (1997-12-01), Miles et al.
Glenn Thomas P.
Jewler Scott J.
Moon D. H.
Roman David
Yee J. H.
Amkor Technology
Chambliss Alonzo
Stetina Brunda Garred & Brucker
Talbott David L.
LandOfFree
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