Methods for maximizing routability in a programmable interconnec

Details Methods for maximizing routability in a programmable interconnec Methods for maximizing routability in a programmable interconnec

1997-10-23

1999-07-13

Teska, Kevin J.

Communications: electrical

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Internal alarm or indicator responsive to a condition of the...

34082583, 307112, G06F 15173, G06F 1716

Patent

active

059238682

ABSTRACT:
Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width w.sub.mux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width w.sub.mux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors. According to a second embodiment, a predictive swapping technique is used whereby successfully routed signals qualified to provide a blocked signal with a route are first checked to determine whether a successful routing will be provided before swapping in the blocked output signal.

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United States Patent Application, Serial No. 08/282,911, filed Jul. 29, 1994, entitled "Methods for Maximizing Routability in a Programmable Interconnect Matrix Having Less Than Full Connectability".
"United States Patent Application No. 08/705,990, filed Aug. 30, 1996, a continuation of Application No. 08/283,650, filed Aug. 1, 1997, entitled Methods for Maximizing Routability in a Programmable Interconnect Matrix Having Less Than Full Connectability."

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