Methods for manufacturing electronic and electromechanical...

Details Methods for manufacturing electronic and electromechanical... Methods for manufacturing electronic and electromechanical...

2000-03-03

2002-02-19

McPherson, John A. (Department: 1756)

Radiation imagery chemistry: process, composition, or product th

Visible imaging including step of firing or sintering

C430S311000, C430S315000, C430S031000, C430S545000, C427S096400, C427S554000, C427S559000

Reexamination Certificate

active

06348295

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to fabrication of electronic and electromechanical devices, and in particular to fabrication of such devices by controlled particle deposition and patterning.
BACKGROUND OF THE INVENTION
Electronic and electromechanical components are presently fabricated in large, immobile manufacturing facilities that are tremendously expensive to build and operate. For example, semiconductor device fabrication generally requires specialized microlithography and chemical etching equipment, as well as extensive measures to avoid process contamination.
The large up-front investment required for manufacturing capacity not only limits its general availability, but also increases the cost of custom fabrication. For a small custom order to be financially competitive with mass production of an established device, the per-unit cost will necessarily be quite high—often out of reach for many designers. Currently, the economics of device fabrication disfavors sophistication and small batch sizes.
In addition to their expense, the fabrication processes ordinarily employed to create electronic and electromechanical components involve harsh conditions such as high temperatures and/or caustic chemicals, limiting the ability to integrate their manufacture with that of functionally related but environmentally sensitive elements. For example, the high temperatures used in silicon processing may prevent three-dimensional fabrication and large-area fabrication; these temperatures are also incompatible with heat-sensitive materials such as organic and biological molecules. High temperatures also preclude fabrication on substrates such as conventional flexible plastics, which offer widespread availability and low cost.
These fabrication processes are also subtractive, depositing a desired material over an entire substrate before removing it from undesired locations through techniques such as etching and lift-off. Subtractive processes are wasteful; introduce dangerous, costly, and environmentally unfriendly chemicals to the fabrication process; and limit the range of manufacturable devices since the etch chemistry can interact with previously deposited layers.
Despite intensive effort to develop alternatives to these processes, no truly feasible techniques have yet emerged. U.S. Pat. No. 5,817,550, for example, describes a low-temperature roll-to-roll process for creating thin-film transistors on plastic substrates. This approach faces numerous technical hurdles, and does not substantially reduce the large cost and complexity associated with conventional photolithography and etching processes.
U.S. Pat. No. 5,772,905 describes a process called “nanoimprint lithography” that utilizes a silicon mold, which is pressed under high pressure and temperature into a thin film of material. Following cooling with the mold in place, the material accurately retains the features of the mold. The thin film may then be treated to remove the small amount of material remaining in the embossed areas. Thus patterned, the film may be used as a mask for selectively etching underlying layers of functional materials. This process is capable of producing patterns with very fine resolutions at costs significantly below those associated with conventional processes. But it is quite complicated, requiring numerous time-consuming steps to create a single layer of patterned functional material. The technique requires high application pressures and temperatures at very low ambient pressures, thereby imposing significant complexity with attendant restriction on the types of materials that can be patterned. Perhaps most importantly, this technique is limited to producing single-layer features, thereby significantly limiting its applicability to device fabrication.
U.S. Pat. No. 5,900,160 describes the use of an elastomeric stamp to mold functional materials. In particular, the stamp is deformed so as to print a self-assembled molecular monolayer on a surface. This process, also called MIMIC (Micromolding Against Elastomeric Masters), is significantly simpler than nanoimprint lithography, and can be performed at ambient temperatures and pressures. But the technique is generally limited to low-resolution features (in excess of 10 &mgr;m), and more importantly, the types of geometries amenable to molding by this technique are limited.
DESCRIPTION OF THE INVENTION
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, an electrically (and, possibly, mechanically) active pattern is applied using a colloidal suspension of nanoparticles that exhibit a desired electrical and/or mechanical characteristic. The nanoparticles are surrounded by an insulative shells that may be removed by therefrom by application of energy (e.g., in the form of electromagnetic radiation or heat). The nanoparticle suspension is applied to a substrate (or to a layer previously formed in accordance herewith), forming a layer that is substantially insulative owing to the nanoparticle shells. The layer may be in the form of a continuous planar film or may instead assume a desired pattern.
The applied suspension is exposed to energy to remove the capping groups and fuse the particles into cohesion. If the nanoparticle suspension was deposited as a uniform film, the energy is applied in a desired pattern so that unexposed areas remain insulative while exposed areas exhibit the electrical behavior associated with the nanoparticles. If the nanoparticle suspension was deposited in a desired pattern, it may be uniformly exposed to energy. Additional layers may be applied in the same manner, one over the other, to form a multilayer device.
The nanoparticle suspension may be applied by any of numerous suitable techniques. Spin coating may be used to form a uniform film of the suspension, while ejection (e.g., ink-jet), transfer techniques, or electrostatic patterning can be used to create patterns. Moreover, various techniques may be used to deliver energy to the deposited suspension.


REFERENCES:
patent: 4298448 (1981-11-01), Muller et al.
patent: 5066559 (1991-11-01), Elmasry et al.
patent: 5380362 (1995-01-01), Schubert
patent: 5559057 (1996-09-01), Goldstein
patent: 5587111 (1996-12-01), Watanabe et al.
patent: WO-97/38810 (1997-10-01), None
Guo, et al., “A room-temperature silicon single-electron metal-oxide-semiconductor memory with nanoscale floating-gate and ultranarrow channel,” Appl. Phys. Lett. 70(7), pp. 850-852, Feb. 17, 1997.
Zhuang, et al., “Silicon single-electron quantum-dot transistor switch operating at room temperature,” Applied Physics Letters, vol. 72, No. 10, pp. 1205-1207, Mar. 9, 1998.
Guo, et al., “Fabrication and characterization of room temperature silicon single electron memory,” J. Vac. Sci. Technol. B 15(6), pp. 2840-2843, Nov./Dec. 1997.
Yano, et al., “SA 21.7:A 128 Mb Early Prototype for Gigascale Single-Electron Memories,” IEEE International Solid-State Circuits Conference, 1998.
Ishii, et al., “Verify: Key to the Stable Single-Electron-Memory Operation,” IEEE, IEDM 97, pp. 171-174, 1997.
Yano, et al., “FP 16.4: Single-Electron-Memory Integrated Circuit for Giga-to-Tera Bit Storage,” IEEE International Solid-State Circuits Conference, 1996.
Nakajima, et al., “Room Termperature Operation of Si Single-Electron Memory with Sel-Aligned Floating Dot Gate,”IEDM 96,PP. 952-954, 1996.
Tiwari, et al., “Technology and Power-Speed Trade-offs in Quantum-dot and Nano-crystal Memory Devices,”Symposium on VLSI Technology Digest of Technical Papers,pp. 133-134, 1997.
Bhyrappa, et al., “Hydrogen-Bonded Porphyrinic Solids: Supramolecular Networks of Octahydroxy Porphyrins,”J. Am. Chem. Soc.,vol. 119, 8492-8502, 1997.
Zollinger,Color Chemistry,2nded., Weinheim, New York, pp. 352-361, 1991.
Murray et al., “Self-Organization of CdSe Nanocrystallites into Three-Dimensional Quantum Dot Superlattices,”Science,vol. 270, pp. 1335-1338, Nov. 24, 1995.
Terris, et al., “Near-field optical data storage using a solid immersion lens,”Appl. Phys. Lett.,vol. 65, No. 4, pp. 388-390, Jul. 25, 1994.
Markovich, et al., “P

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