Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-10-14
2004-12-07
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S430000, C438S435000, C438S443000, C438S444000
Reexamination Certificate
active
06828209
ABSTRACT:
Japanese patent application no. 11-294126, filed Oct. 15, 1999, is hereby incorporated by reference in its entirety.
TECHNICAL FIELD
The present invention relates to devices and methods for manufacturing semiconductor devices, and more particularly, to devices and methods for manufacturing semiconductor devices having element isolation regions.
BACKGROUND
In recent years, with a further miniaturization of MOS transistors being pursued, a further miniaturization of a region for isolating semiconductor elements from one another is needed. In order to achieve the miniaturization of the region, a variety of trench element isolation techniques are considered. In a typical trench element isolation technique, a trench is provided on a substrate between semiconductor elements, and an insulation material is filled in the trench to isolate the semiconductor elements from one another. One example of the technique is described below.
FIGS. 34 through 37
schematically show in cross section steps of forming a trench element isolation region
123
in which a conventional trench element isolation technique (hereafter referred to as “conventional technique”) is conducted.
First, as shown in
FIG. 34
, a pad layer
112
and a stopper layer
114
are successively deposited on a silicon substrate
110
. Then, a resist layer R
10
having a specified pattern is formed on the stopper layer
114
. The stopper layer
114
and the pad layer
112
are etched, using the resist layer R
10
as a mask.
Then, as shown in
FIG. 35
, the resist layer R
10
is removed by an ashing step. Then, the silicon substrate
110
is etched, using the stopper layer
114
as a mask to form a trench
116
. Then, an exposed surface of the silicon substrate
110
in the trench
116
is thermally oxidized to form a trench oxide film
118
.
Then, as shown in
FIG. 36
, an insulating layer
120
is deposited over the entire surface in a manner to embed the trench
116
. Then, the insulating layer
120
is planarized, using the stopper layer
114
as a stopper. Then, the stopper layer
114
is removed by using a heated phosphoric acid.
Then, protruded portions
122
of the insulating layer are isotropically etched by an etchant including a hydrofluoric acid. As a result, the trench element isolation region
123
shown in
FIG. 37
is formed. It is noted that the protruded portions
122
of the insulating layer are portions of the insulating layer
120
that protrude from the surface of the silicon substrate
110
in a region where elements are formed.
However, according to the conventional technique, the following problems occur.
FIG. 38
schematically shows an expanded view of a portion C of FIG.
37
. When the protruded portions
122
of the insulating layer are isotropically etched, a recess
125
is generated in an upper end section of the insulating layer
120
. The further the protruded portions
122
of the insulating layer are isotropically etched, the deeper the recess
125
becomes. As the recess
125
becomes deeper, the trench oxide layer
118
is gradually removed in the depth direction of the trench
116
due to the following reasons. As the recess
125
becomes deeper, the trench oxide film
118
is more exposed in the direction of the depth of the trench
116
. The trench oxide film
118
and the insulating layer
120
are formed from the same materials, such as silicon oxide. Therefore, the exposed portion of the trench oxide film
118
comes in contact with the etchant, and is isotropically etched. As a result, the deeper the recess
125
becomes, the deeper the trench oxide film
118
is removed in the depth direction. When the trench oxide film
118
is removed and the trench oxide film
118
becomes thinner, problems in the transistor characteristics, such as the inverse narrow channel effect, humps and the like, occur.
SUMMARY
One embodiment relates to a method for manufacturing a semiconductor device having a trench element isolation region including a trench and a trench insulating layer that fills the trench, the method including the steps of (A) forming a polishing stopper layer over a substrate, the polishing stopper layer having a predetermined pattern for a chemical-mechanical polishing; (B) removing a part of the substrate using a mask layer including at least the polishing stopper layer as a mask to form a trench; (C) forming a trench oxide film over a surface of the substrate that forms the trench; (D) forming an insulating layer that fills the trench over an entire surface of the substrate; (E) polishing the insulating layer by a chemical-mechanical polishing; (F) removing the polishing stopper layer; and (G) etching a part of the insulating layer to form a trench insulating layer, wherein the method further includes the step (a) of forming an etching stopper layer for the trench oxide film over at least a portion of the trench oxide film and wherein, in the step (G), the etching stopper layer is more resistant to the etching than the insulating layer.
Another embodiment relates to a semiconductor device comprising trench element isolation regions, wherein at least one of the trench element isolation regions has a trench oxide film formed on a surface of a substrate that forms a trench and a trench insulating layer formed in the trench, wherein an etching stopper layer is formed such that a surface of the trench oxide film on a side wherein the trench insulating layer is formed is not exposed.
Another embodiment relates to a semiconductor device comprising trench element isolation regions, wherein at least one of the trench element isolation regions includes a trench oxide film formed on a surface of a substrate that forms a trench and a trench insulating layer formed in the trench. The device also includes an etching stopper layer formed between the trench oxide film and the trench insulating layer.
Still another embodiment relates to a method for manufacturing a semiconductor device, including forming a trench comprising a lower surface and two side surfaces in a substrate comprising silicon and forming a trench oxide layer on the lower surface and side surfaces. The method also includes forming an etch stop layer in direct contact with the trench oxide layer on the lower surface and side surfaces, and filling the trench with an insulating layer directly contacting the etch stop layer, wherein the insulating layer overfills the trench and extends above the trench as defined by the two side surfaces. The method also includes etching the insulating layer using an etchant that selectively etches the etch stop layer at a rate that is slower than that of the insulating layer.
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patent: 4571819 (1986-02-01), Rogers et al.
patent: 4952524 (1990-08-01), Lee et al.
patent: 5275965 (1994-01-01), Manning
patent: 5387540 (1995-02-01), Poon et al.
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patent: 5741740 (1998-04-01), Jang et al.
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patent: 6046487 (2000-04-01), Benedict et al.
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patent: 6146970 (2000-11-01), Witek et al.
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patent: 9-82956 (1997-03-01), None
patent: 11-087490 (1999-03-01), None
patent: 2000-031264 (2000-01-01), None
Japan Office Action for Japanese Patent Application No. 11-294126 (from which priority is claimed for 09/687,197) dated Mar. 23, 2004 (which lists 9-82956 cited above).
Notice of Reasons of Rejection for Japanese Patent Application No. 11-294126 (from which priority is claimed in U.S. Ser. No. 09/687,197), dated Apr. 8, 2003, which lists JP11-087490 and JP10-193037 (JP2000-031264).
Duong Khanh
Konrad Raynes & Victor LLP
Raynes Alan S.
Seiko Epson Corporation
Trinh Michael
LandOfFree
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