Methods for making z-axis electrical connections

Metal working – Method of mechanical manufacture – Electrical device making

Reexamination Certificate

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C029S834000, C174S260000, C174S261000, C257S737000, C257S738000, C361S760000, C428S343000, C428S356000, C439S068000

Reexamination Certificate

active

06260264

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally methods and apparatuses for forming electrical connections. More specifically, the present invention relates to methods and apparatuses for making z-axis electrical connections between integrated circuit chips and their packaging circuits.
BACKGROUND OF THE INVENTION
The vast majority of electronic circuit assemblies in the world today utilize integrated circuit (IC) chips which have been housed in protective packages. These packages provide mechanical and sometimes thermal protection for the chips while also providing an intermediate level of interconnection between the chips and printed circuit boards. Years ago, package sizes were large compared to the size of chips. In part this was necessary because attainable feature sizes for printed circuit boards (PCB) were very large compared to those of chips. Over time, the ability to produce fine-featured circuit boards has improved and package sizes have correspondingly decreased relative to IC size. However, because of the needs to cut costs and reduce circuit size and improve performance, there has been a drive to develop circuit assembly methods which minimize the materials and processes which are required to yield a functional device.
One technique used to reduce circuit size and improve performance involves attaching IC devices directly to a substrate using perimeter or area arrays of solder balls mounted on the face of a chip. By inverting or “flipping” the chip such that the balls are placed in contact with pads on the substrate and passing the entire assembly through a solder reflow process, the IC may be metallurgically bonded to the substrate. Although flip-chip assembly technology was first pioneered over 30 years ago, it has been successfully exploited in only a few different segments of the electronics industry. The most notable examples of electronic products which have exploited flip-chip assembly include wristwatches, automotive sensors/controllers and mainframe computers. These applications are characterized by the need for either extremely compact circuit size (watches, automotive) or by extremely high computing power per unit volume (mainframes). This underscores the simple fact that by eliminating the intermediate IC package, flip-chip assembly provides the smallest possible footprint for silicon on the circuit board.
A primary reason why flip-chip technology has not enjoyed a more widespread use is because the methodology, as it has currently been developed, is extremely process and equipment intensive. As a result, flip-chip technology is expensive to implement and provides many opportunities for problems to arise. In addition, process and performance requirements of the applications have reached the limits of current materials.
Existing flip-chip technology utilizes chips for which solder has been preapplied to the interconnection pads. The solder is normally either a 95Pb-5Sn or a 63Sn-37Pb alloy, and it is normally reflowed to form a nearly spherical “bump” prior to final board assembly.
A typical assembly process for flip-chip assembly involves the following steps: 1) flux paste is applied to the substrate bond pads; 2) the IC is aligned and placed on the substrate while the tackiness in the flux holds the chip in place; 3) the assembly is passed through the reflow oven and the solder melts and bonds metallurgically with the substrate pads; and 4) the sample is passed through a flux cleaning operation. Flux removal has normally been done with solvent rinses. Originally it was required to use chlorinated solvents to remove the flux residues, but more recently improvements to the flux chemistry has permitted the use of more desirable solvents.
The finished flip-chip assembly must then maintain electrical continuity throughout the lifetime of the device as measured by accelerated tests such as thermal cycling and thermal shock. Mismatches of both the coefficient of thermal expansion (CTE) and the elastic modulus (E) between the silicon IC and the PCB generate high stresses in the contact joints when the circuit is passed through thermal excursions. These stresses can lead to solder joint fatigue failure after repeated temperature cycles, and this is a primary failure mechanism for flip-chip joints. This mechanism has limited the selection of substrate materials mainly to ceramic hybrid substrates such as Al
2
O
3
, which has high modulus and low CTE, properties similar to silicon. Even with ceramic substrates, flip-chip assembly is limited to applications with small dice.
During the last ten to fifteen years there has been increasing interest in learning how to apply this flip-chip assembly to both larger size die and also to a broader range of printed circuit substrates. Specifically the increased wiring densities available with today's organic based substrates makes them suitable low cost substitutes for ceramic substrates. However, the relatively high CTE of organic materials has slowed the implementation of flip-chip assembly on organic substrates due to the aforementioned failure mechanism. An important breakthrough has been the development of underfill process. Underfill process uses a high modulus curable adhesive to fill the empty space between the solder balls under the chip so that the stress in the joint is shared by the adhesive and distributed more evenly across the entire interface as opposed to being concentrated at the perimeter balls. The use of an “underfill” adhesive as described above has enabled a flip-chip technology to be applied to a broader range of assemblies.
In current practice, underfill resin is applied as a liquid and is allowed to wick under the reflowed assembly. The current procedure for applying and curing underfill resins is separate from and is appended to the overall process sequence described above. After the reflow and flux removal steps, it is necessary to: pre-dry the bonded assembly, preheat the bonded assembly (to aid the wick-under), dispense resin, allow resin to wick under the die, dispense again, and then cure. Currently available underfill resins require cures of up to 2 hours at 150° C. The extra dispense steps are often needed in order to make sure that there is no entrapped air under the chip and also to provide a good fillet shape. Developing and maintaining good control over these types of material characteristics and dispensing processes is very difficult, and any imperfections will hurt the reliability of the solder joints.
Recently, an alternative approach for applying underfill resin has been pursued in which the uncured liquid resin is actually dispensed prior to the chip placement. In this case, special adhesive formulations are used that are capable of providing some degree of a fluxing action as they cure in the reflow oven. Because the resin is present on the board before the chip is placed, it is necessary to press the chip down into the resin and displace the resin from the contact sites. This approach eliminates an extra adhesive curing step, and also eliminates the subsequent dispense and wick-under step. However, it has been shown that in order for this approach to work, the underfill resin must be unfilled. The inability to utilize fillers in the underfill resin is a constraint that substantially limits the utility of this approach. See, for example, U.S. Pat. No. 5,128,746, Shi et al., High Performance Underfills for Low-Cost Flipchip Applications Proc. 3d Int'l Symp. On Adv. Packaging Materials, March 1997; Gamota et al., Advanced Flipchip Materials: Reflowable Underfill Systems, Proc. Pac. Rim ASME Int'l Intersociety Electronic and Photonic Packaging Conf., ASME, June 1997; Johnson et al., Reflow Curable Polymer Fluxes for Flipchip Assembly, Proc. Surface Mount Int'l 1997.
The choice of chemistry for the underfill adhesive is constrained by the processing and performance requirements stated above. For best fatigue performance, it is best to choose materials that have the highest modulus and lowest CTE over the temperature range of the thermal cycling. Fo

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