Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates
Reexamination Certificate
1998-03-09
2001-02-27
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
C438S107000, C438S118000, C438S109000
Reexamination Certificate
active
06194290
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductors, and, more particularly, to a method of fabricating power semiconductor devices, and the devices produced by the method.
BACKGROUND OF THE INVENTION
Electronic power switching devices are widely used in many applications, such as, for example, motor controls, inverters, line switches, pulse circuits, and other power switching applications. A silicon controlled rectifier (SCR) or thyristor is a bistable semiconductor switching device formed from four layers of silicon. One type of power switching device, the MOS controlled thyristor (MCT) is especially suited for resonant (zero voltage or zero current switching applications. The MCT has a forward voltage drop much like the SCR, and therefore enjoys greatly reduced conduction power loss. The MCT allows the control of high power circuits with very small amounts of input energy—a feature common to SCRs as well. In an MCT, turn-off is accomplished by turning on a highly interdigitated off-FET to short out one or both of the emitter-base junctions of a thyristor.
Another advantageous power switching device is the insulated gate bipolar transistor (IGBT) which is designed for high voltage, low on-dissipation applications, such as switching regulators and motor drivers. The IGBT can be operated from low power integrated circuits. The IGBT is also an insulated gate, field controlled switching device like the MCT. Available MCTs and IGBTs are useful at high switching frequency than is generally practice with power Darlington transistors, for example. In addition, both may be operated with junction temperatures of 150° C. and above, and operate in switching circuits having 600 volts or higher switch ratings.
One approach to fabricating power switching devices involves direct semiconductor-semiconductor wafer bonding. The wafer bonding has been for the purpose of replacing a thick, e.g. 100 &mgr;m epitaxial layer growth. For this bonding application, high temperature bonding anneals at temperatures of greater than about 1100° C. are typically used to remove microvoids and bubbles. Both hydrophobic and hydrophilic bonding has been used.
Recently there has been increasing interest in the possibility of fabricating switching power devices with MOSFET current control devices on both the front side and back side of the power device to achieve faster turnoff of the device such as disclosed in U.S. Pat. No. 4,977,438 to Abbas. The conventional approach for fabricating double-sided MOSFET controlled power devices is to perform processing and photosteps on both sides of the wafer. This approach required critical control of thermal budgets, has approximately a factor of two increase in fabrication steps, and increases the possibility of yield loss due to scratches, etc.
U.S. Pat. No. 5,541,122 to Tu et al., for example, discloses a fabrication method for an IGBT wherein two wafers are bonded together, and annealed at a temperature in a range of 800 to 1100° C. An N-type wafer is doped N+ at a surface thereof and is bonded to a P+ wafer to define an N+ buffer region for the IGBT. Thereafter, a gate is formed on the upper surface and various diffusions are also made adjacent the gate to define an emitter/collector encircling the gate. An emitter contact is formed on the diffusions and a collector contact is deposited on the lower surface of the wafer using conventional techniques.
Unfortunately, the relatively high temperature annealing and subsequent device processing steps may adversely affect the doping profile of the buffer layer. Accordingly, the turnoff speed may be reduced. In addition, the double-sided processing after annealing requires a relatively large number of process steps, and the substrates are subject to mechanical damage which may reduce yields.
SUMMARY OF THE INVENTION
In view of the foregoing background, it is therefore an object of the present invention to provide methods for forming power devices with reduced process steps and/or improved device quality.
These and other objects, features and advantages in accordance with the present invention are provided by a method for making a semiconductor device from a plurality of semiconductor substrates, and wherein the method comprises the steps of: processing at least one surface of at least one of the substrates; bonding the processed substrates together so that the at least one processed surface defines an outer surface of the semiconductor device; and annealing the bonded together substrates at a relatively low anneal temperature so as to not adversely effect the processed surface. The step of processing may comprise forming a metal layer, and, accordingly, the anneal temperature is preferably less than a temperature related to a characteristic of the metal layer, such as a melting temperature or a reaction temperature with the substrate.
The step of processing may comprise forming an aluminum layer. Thus, the anneal temperature may be less than about 450° C. The method may further comprise the step of forming a barrier metal between the aluminum and substrate, and, the anneal temperature may be in a higher range of about 450 to 550° C.
One aspect of the invention is that the step of processing preferably comprises forming at least one doped region. In this embodiment, the metal may be added after bonding and annealing, and the anneal temperature is preferably less than about 900° C., and, more preferably, less than about 800° C.
Another aspect of the invention relates to the ability of the bonded together substrates to be cut or diced. The anneal temperature is preferably sufficient to provide a predetermined surface energy to permit cutting. For example, the anneal temperature may be greater than about 400° C., and the predetermined surface energy may be greater than about 800 ergs/cm
2
.
The substrates in some embodiments may be silicon thus, the method preferably further comprises the step of hydrogen terminating the silicon surfaces prior to the bonding step, such as by cleaning.
In one advantageous embodiment of the invention, the step of processing preferably comprises completely processing the at least one substrate to form all active devices and interconnections. The processing step may comprise forming at least one MOSFET control device as may be useful for an IGBT or MCT. Moreover, the plurality of substrates may be two, and the processing step may comprise processing both substrates prior to bonding and annealing.
REFERENCES:
patent: 4233103 (1980-11-01), Shaheen
patent: 4784872 (1988-11-01), Moeller et al.
patent: 4977438 (1990-12-01), Abbas
patent: 4994884 (1991-02-01), Kato et al.
patent: 5027180 (1991-06-01), Nishizawa et al.
patent: 5270230 (1993-12-01), Sakurai
patent: 5323059 (1994-06-01), Rutter et al.
patent: 5426314 (1995-06-01), Nishizawa et al.
patent: 5459339 (1995-10-01), Sakurai et al.
patent: 5493134 (1996-02-01), Mehrotra et al.
patent: 5506153 (1996-04-01), Brunner et al.
patent: 5541122 (1996-07-01), Tu et al.
patent: 5608237 (1997-03-01), Aizawa et al.
patent: 5767001 (1998-06-01), Bertagnolli et al.
patent: 5855693 (1999-01-01), Murari et al.
patent: 5915193 (1999-06-01), Tong et al.
patent: 5927993 (1999-07-01), Lesk et al.
Hobart Karl
Kub Francis J.
Neilson John
Temple Victor
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Berezny Neal
Fahmy Wael
Intersil Corporation
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