Methods for making neighboring wells for VLS1 CMOS components

Details Methods for making neighboring wells for VLS1 CMOS components Methods for making neighboring wells for VLS1 CMOS components

1987-04-02

1989-02-07

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 69, 437239, 437241, 437228, 437233, 148DIG117, 156653, 156657, H01L 21308

Patent

active

048031798

ABSTRACT:
A method for the manufacture of neighboring wells 9, implanted with dopant ions of differing conductivity type in silicon substrates provided with an epitaxial layer. A lateral under-etching having high selectivity to specified layers is designationally introduced into a silicon nitride layer provided for masking the n-well regions in the implantation of the p-wells. Thus, the edge of a silicon oxide layer serving as a masking in the following oxidation shifts in the direction of the n-wells. As a result of this type of self-adjusted well production, the influence of the counter-doping in the region of the well boundaries is noticeably reduced. In addition, a polysilicon layer can also be employed under the silicon nitride layer as a masking layer, this layer eing co-oxidized after the under-etching of the silicon nitride layer. Thus a box-shaped course is produced in the masking oxide instead of the prior art bird's bill course, whereby a steeper diffusion front is achieved in the n-well. The method serves for the manufacture of VLS1 complementary MOS field effect transistor circuits.

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