Methods for isolating interconnects

Details Methods for isolating interconnects Methods for isolating interconnects

1998-12-17

2001-04-24

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Liquid phase etching

C438S750000, C438S753000, C438S754000

Reexamination Certificate

active

06221786

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to methods for isolating interconnects. In particular, it relates to methods for isolating interconnects by means of air instead of traditional low-k dielectric materials.
BACKGROUND OF THE INVENTION
With the increasing integration of ICs, chips can not provide an enough surface area to produce interconnects. Therefore, the multiple metal layers design rule is provided to produce interconnects of MOS transistors with narrowed-down line-width, especially in products with complex functions. For example, four or five metal layers used to connect devices are present in a microprocessor.
The multiple-interconnects are formed when the MOS is finished; therefore, the process for producing multiple-interconnects can be viewed as an independent semiconductor process. Among the multiple interconnects, the orientations of two independent interconnects are crossed-over each other; moreover, a dielectric layer isolating two independent interconnects is used to avoid shorts resulting from the contact of independent interconnects. The dielectric layer used to isolate interconnects is also known as the inter-metal dielectric (IMD) layer. In addition, the independent interconnects can be conducted by a traditional plug. As shown in FIG.
1
A and
FIG. 1B
, a substrate
100
comprising a number off semiconductor devices was provided first. Then, a low-k insulating layer
110
, i.e. a silicon oxide layer, was formed over the substrate
100
. Subsequently, an interconnect
120
consisting of a plurality of metal lines isolated from each other was formed over the insulating layer
110
by a traditional metallization process. Then, another interconnect
130
consisting of a plurality of metal lines with an orientation crossing-over the interconnect
120
was formed over the insulating layer
130
. By means of the method described above, the interconnects
120
and
140
were isolated by the low-k insulating layer
110
.
The dielectric materials suitable for application in the isolation process as described above include silicon oxide (with a dielectric constant 4~5), TEOS (with a dielectric constant 4~5), silicon nitride (with a dielectric constant 6~9), silicon nitroxide, phosphorus silicon glass (PSG) and boron-phosphorus silicon glass (BPSG). During the 0.32 &mgr;m process, the average dielectric constant of dielectric materials described above is about
4
. In order to reduce the increasing RC-delay effect resulting from the narrowing distance between interconnects, it is necessary to develop a novel method for isolating the interconnects by using a low-k material (k<3).
SUMMARY OF THE INVENTION
In order to provide a low-k dielectric layer for isolating the interconnects, the present invention uses air instead of the traditional low-k dielectric materials to isolate the interconnects.
The feature of the invention is providing a method for isolating interconnects, the steps comprising: providing a substrate; forming a first insulating layer over the substrate; forming a first interconnect over the first insulating layer; forming a first stop layer overlying over the first interconnect and the first insulating layer; forming a second insulating layer over the first stop layer; forming a photoresist pattern layer over the second insulating layer; using the photoresist pattern layer as a mask and etching the exposed second insulating layer to the first stop layer to define two bridge-supporting structures beside the first interconnect; forming a second stop layer overlying over the first stop layer and the bridge supporting structures; forming an intermetal-dielectric layer with a thickness more than that of the bridge-supporting structures over the second insulating layer; applying a planarization treatment by etching back the intermetal-dielectric layer to the second stop layer on the bridge-supporting structures; forming a third stop layer over the second inter-metal dielectric layer; forming a second interconnect over the third stop layer, wherein the orientation of the second interconnect crosses-over the first interconnect; forming a passivation layer overlying the second interconnect and the third stop layer; defining at least one channel through the passivation layer, the third stop layer, the second layer and exposing the inter-metal dielectric layer; dissolving the inter-metal dielectric layer completely with a suitable solvent through the channel to form a chamber for isolating the first and second interconnects.
In the isolation method described above, the first and the second insulating layers are selected from the group consisting of silicon oxide, TEOS, SOG, BPSG and PSG. The first interconnect and the second interconnect can consist of aluminum, copper, Al—Cu alloy or Al—Cu—Si alloy. The inter-metal dielectric layer (IMD) consists of a low-k dielectric material, such as silicon oxide, TEOS, PSG and BPSG. The first insulating layer, the second insulating layer, the third insulating layer and the passivation layer can consist of silicon nitride (Si
3
N
4
) or silicon oxynitride (SiO
x
N
y
). Moreover, an extra drying step can be performed to evaporate the water and solvent in the chamber after the inter-metal dielectric layer is dissolved completely by the suitable solvent, then sealing the channel. In addition, an inert gas such as nitrogen or a noble gas can be directed into the chamber before the channel is sealed.
Other features and advantages of the invention will be apparent from the following detailed description, and from the claims.


REFERENCES:
patent: 5141896 (1992-08-01), Katoh
patent: 5510645 (1996-04-01), Fitch et al.
patent: 5559055 (1996-09-01), Chang et al.
patent: 5759913 (1998-06-01), Fulford et al.
patent: 5782984 (1998-07-01), Lim et al.
patent: 5783864 (1998-07-01), Dawnson et al.
patent: 5968851 (1999-10-01), Geha et al.

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