Methods for inspecting and optionally reworking summed...

Details Methods for inspecting and optionally reworking summed... Methods for inspecting and optionally reworking summed...

2007-11-21

2010-11-09

Huff, Mark F (Department: 1795)

Stock material or miscellaneous articles

Circular sheet or circular blank

C428S195100

Reexamination Certificate

active

07829168

ABSTRACT:
A batch of wafers is temporarily stalled during a Double Pattern Technology (DPT) process before a temporary representation of a second of to-be-overlaid patterns is permanently combined with a first of the patterns. Sampled ones of the stalled wafers are inspected to determine if sufficiently close alignment is present between the two patterns. If excessive misalignment is detected (e.g., by SEM microscopy), the second but still temporary pattern representation is erased from all wafers of the batch and the batch is routed for rework and corrected reestablishment of the temporary representation of the second of to-be-overlaid patterns.

REFERENCES:
patent: 5252414 (1993-10-01), Yamashita et al.
J. Allgair et al., “Taking Aim at the Overlay Metrology Budget for 70 nm,” Yield Management Solutions, 2003, pp. 29-34.
B. Schultz et al., “In-chip Overlay Metrology in 90-nm Production,” Yield Management Solutions, 2006, pp. 60-63.
M. Dusa et al., “Pitch Doubling Through Dual Patterning Lithography Challenges in Integration and Litho Budgets”, Optical Microlithography XX, Proc. of SPIE vol. 6520, 65200G (2007, before the filing date Nov. 21, 2007 of the present application), pp. 65200G-1 through 65200G-10.

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