Methods for implementing co-axial interconnect lines in a...

Details Methods for implementing co-axial interconnect lines in a... Methods for implementing co-axial interconnect lines in a...

1999-10-28

2003-04-08

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S787000, C257S659000

Reexamination Certificate

active

06545338

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the manufacture of semiconductor devices. More particularly, the present invention relates to the integration of radio frequency (RF) devices and RF features and microwave devices and microwave features into standard complementary metal oxide semiconductor (CMOS) chips.
2. Description of the Related Art
Today's semiconductor devices are continually being pushed to meet stricter demands. As devices using this technology inundate the marketplace, consumers place higher demands on the devices. These demands include smaller, more compact devices with greater functionality.
In order to meet the demands, semiconductor devices employ CMOS chips and RF chips. Such devices include, for example, cellular phones that require both digital CMOS circuitry as well as RF circuitry to enable wireless communication. Conventionally, in order to integrate both digital CMOS and RF circuitry onto one chip, manufacturers have been forced to use co-axial interconnect lines to handle the RF signals.
In addition, the use of a co-axial interconnect line presents other problems.
FIGS. 1A and 1B
represent a cross-sectional view and a top view, respectively, of a prior art interconnect structure
12
having a suspended portion
14
over a silicon substrate
10
. Interconnect structure
12
includes an inner conductor
20
, an insulating dielectric coating
18
and an outer conductive layer that serves to encapsulate the insulating dielectric coating
18
. Interconnect structure
12
also includes two contact posts
13
fabricated that have a larger dimension so as to support suspended portion
14
.
It should be noted that the suspended portion
14
tends to sag under the influence of gravity. Therefore, there is a limit to the length of such structures before they fracture and break, which is a significant practical problem in implementing this prior art structure. Another problem encountered with the interconnect structure of
FIG. 1A
is the inability to stack multiple interconnect layers. By way of example, if a second interconnect structure were built over structure
12
, the probability of breaking center region
14
dramatically increases due to the lack of mechanical support under center region
14
. For a more detailed description of the steps associated with fabricating this prior art interconnect structure, reference may be made to a paper entitled “VLSI Multilevel Micro-Coaxial Interconnects for High Speed Devices” by M. E. Thomas, et al., Fairchild Research Center, National Semiconductor Corporation, Santa Clara, Calif., IEDM Tech. Dig., pages 55-58. (1990), which is hereby incorporated by reference.
Another drawback of integrating RF circuitry into chips that are primarily designed for digital CMOS circuits is co-axial lines
12
must be integrated at the top-most metallization level of a chip. This presents significant limitations in the number of RF lines that can be used to complete RF signal processing for a given chip. Therefore, designers wanting to integrate RF lines over predominately CMOS chips must design the chip substantially larger to enable the desired number of RF lines to appropriately be integrated to the top metal layer of the chip. This limitation is well known to circuit designers, and therefore, it is often determined to be more advantageous to use separate chips for CMOS circuitry and RF circuitry.
As shown in
FIG. 1C
, designers of cellular phones typically find it more practical to use a CMOS chip
52
for performing digital signal processing and a separate RF circuit
55
to process RF signals. This is commonly preferred due to the limitations of trying to integrate RF lines onto chips that are custom fabricated for CMOS digital processing. Nonetheless, an arrangement of this sort presents problems, among them fabrication costs, power losses, signal losses and additional packaging complexities. Circuit
50
requires that RF circuit
55
and the CMOS chip
52
be individually fabricated and integrated onto the printed circuit board (PCB)
51
. This increases manufacturing costs and manufacturing time.
As signals are communicated back and forth from RF circuit
55
and CMOS chip
52
, signal loss will naturally occur. Henceforth, this signal loss reduces overall efficiency of a circuit implementation needing both digital CMOS and RF circuitry. In order to overcome these losses, signal conditioning may be necessary to improve signal integrity. However, the use of such devices will aggravate the problem of packaging that already exists with the prior art.
Packaging inefficiencies of the prior art circuit using RF circuit
55
and CMOS chip
52
make this type of circuit undesirable. In order to integrate separate RF circuit
55
along with CMOS chip
52
, greater amounts of space on the PCB will be required, thereby forcing portable electronics (e.g., cellular phones) to be packaged in larger housings.
In view of the foregoing, there is a need for a circuit which integrates an RF circuit with a CMOS chip which avoids the problems of the prior art. This new circuit should be easy to manufacture, maintain power and signal strength, avoid the use of prior art co-axial lines and come in a more space efficient package. Additionally, this circuit should be able to handle high speed applications, including RF and microwave applications.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by providing a circuit which integrates CMOS lines and RF lines, and methods for making the integrated circuit. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Several inventive embodiments of the present invention are described below.
In one embodiment, a method for making an integrated chip with CMOS lines and RF lines is disclosed. The method includes forming a lower metallization layer and then forming a lower dielectric layer over the lower metallization layer. After forming the lower dielectric layer, a metallization line is formed over the lower dielectric layer. An upper dielectric layer is then formed over the metallization line, with an upper metallization layer formed over the upper dielectric layer. Next, oxide spacers are formed along the sides of the lower and upper dielectric layers, the metallization line and the upper metallization layer. Finally, an encapsulating metal layer is deposited over the oxide spacers such that the lower metallization layer, the upper metallization layer and the encapsulating metallization layer define an outer shield of an RF line and the metallization line defines an inner conductor of the same RF line.
In another embodiment, a semiconductor device with CMOS circuitry and RF circuitry fabricated over a substrate is disclosed. The semiconductor device includes a lower metallization layer and a lower dielectric layer disposed over the lower metallization layer. A metallization line is then defined on the lower dielectric layer. An upper dielectric layer is disposed over the metallization line with an upper metallization layer disposed over the upper dielectric layer. Oxide spacers are defined along the sides of the lower and upper dielectric layers, the upper metallization layer and the metallization line. An encapsulating layer is configured to surround the oxide spacers such that the lower metallization layer, the upper metallization layer and the encapsulating layer define an outer shield of an RF line. The metallization line defines an inner conductor of the same RF line.
In yet another embodiment, a method for fabrication of a semiconductor device with CMOS circuitry and RF circuitry fabricated over a substrate is disclosed. A lower conductive shield is formed and a lower dielectric layer is formed within the shield. Once the lower dielectric layer is formed, a center conductor is formed over the lower dielectric layer. An upper dielectric layer is subsequently formed over the center conductor with an upper conduc

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