Semiconductor device manufacturing: process – Making passive device – Resistor
Reexamination Certificate
2011-07-12
2011-07-12
Nguyen, Khiem D (Department: 2823)
Semiconductor device manufacturing: process
Making passive device
Resistor
C438S586000, C438S595000, C438S597000, C257S538000, C257SE21004, C257SE21585, C257SE29001
Reexamination Certificate
active
07977201
ABSTRACT:
In one embodiment, a second metal line embedded in a second dielectric layer overlies a first metal line embedded in a first dielectric layer. A portion of the second dielectric layer overlying the first metal line is recessed employing a photoresist and the second metal line as an etch mask. A doped semiconductor spacer is formed within the recess to provide a resistive link between the first metal line and the second metal line. In another embodiment, a first metal line and a second metal line are embedded in a dielectric layer. An area of the dielectric layer laterally abutting the first and second metal lines is recessed employing a photoresist and the first and second metal lines as an etch mask. A doped semiconductor spacer is formed on sidewalls of the first and second metal lines, providing a resistive link between the first and second metal lines.
REFERENCES:
patent: 4497685 (1985-02-01), Soclof
patent: 4506283 (1985-03-01), Soclof
patent: 4950619 (1990-08-01), Yoon et al.
patent: 5140299 (1992-08-01), Andrews, Jr. et al.
patent: 5817572 (1998-10-01), Chiang et al.
patent: 5886410 (1999-03-01), Chiang et al.
patent: 5976975 (1999-11-01), Joshi et al.
patent: 6271084 (2001-08-01), Tu et al.
patent: 6373118 (2002-04-01), Lewyn
patent: 6573585 (2003-06-01), Arndt et al.
patent: 6611039 (2003-08-01), Anthony
patent: 6690083 (2004-02-01), Mitchell et al.
patent: 6784045 (2004-08-01), Price et al.
patent: 6849561 (2005-02-01), Goundar
patent: 6897528 (2005-05-01), Al-Sarawi
patent: 7344940 (2008-03-01), Kim et al.
patent: 7569845 (2009-08-01), Chen et al.
patent: 7704873 (2010-04-01), Yu et al.
patent: 2007/0029676 (2007-02-01), Takaura et al.
patent: 2008/0067621 (2008-03-01), Chang et al.
patent: 2008/0079102 (2008-04-01), Chen et al.
patent: 2008/0087921 (2008-04-01), Yu et al.
patent: 2008/0237588 (2008-10-01), Lehr
patent: 2009/0011560 (2009-01-01), Aritome
U.S. Office Actions dated Jul. 12, 2010 and Nov. 5, 2010.
Notice of Allowance dated Jan. 4, 2011 issued in related U.S. Appl. No. 12/191,683.
Abadeer Wagdi W.
Chatty Kiran V.
Gauthier Jr. Robert J.
Rankin Jed H.
Robison Robert
Canale Anthony J.
International Business Machines - Corporation
Nguyen Khiem D
Scully , Scott, Murphy & Presser, P.C.
LandOfFree
Methods for forming back-end-of-line resistive semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods for forming back-end-of-line resistive semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods for forming back-end-of-line resistive semiconductor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2696304