Methods for forming a gate and a shallow trench isolation...

Details Methods for forming a gate and a shallow trench isolation... Methods for forming a gate and a shallow trench isolation...

2008-12-11

2011-10-18

Estrada, Michelle (Department: 2829)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S710000, C438S786000, C257SE21218, C257SE21274

Reexamination Certificate

active

08039402

ABSTRACT:
There is provide a method for forming a gate, which can improve the etching uniformity of the sidewalls of the gate, including the following steps: forming a dielectric layer on a semiconductor substrate; forming a polysilicon layer on the dielectric layer; etching the polysilicon layer; performing an isotropic plasma etching process on the etched polysilicon layer by using a mixed gases containing a fluorine-based gas and oxygen gas; and cleaning the semiconductor substrate subjected to the isotropic plasma etching process, thereby forming a gate. there are also provided a method for forming a shallow trench isolation region, which can improve the filling quality of a subsequent spacer and the electrical properties of the resultant shallow trench isolation region by improving the etching uniformity of sidewalls and bottom surface of the shallow trench, and a method for planarizating an etched surface of silicon substrate, which can improve the etching uniformity of the surface of silicon substrate.

REFERENCES:
patent: 6723653 (2004-04-01), Kim
patent: 2007/0148979 (2007-06-01), Lee et al.
patent: 2008/0176761 (2008-07-01), Menchen et al.
patent: 1457503 (2003-11-01), None
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patent: 1770406 (2006-05-01), None
patent: 101075554 (2007-11-01), None
patent: 2006-165032 (2006-06-01), None

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