Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to nonconductive state
Reexamination Certificate
2002-07-03
2004-01-13
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to nonconductive state
Reexamination Certificate
active
06677188
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of electronic devices and more particularly to an improved method for forming a fuse in a semiconductor device.
BACKGROUND OF THE INVENTION
Certain semiconductor devices, such as dynamic random access memories (“DRAMs”) and static random access memories (“SRAMs”), are designed with redundant rows and/or columns of memory cells. If a memory cell of a row/cell is found to be defective during a test, then the defective memory cell is disconnected by blowing a conductive fuse of the row or column containing the defective cell. Having the redundant rows and/or columns allows a designer to disconnect a defective memory cell without reducing the number of rows/columns below the required number. Typically, a conducting fuse is made of a polysilicon or metal film formed on a dielectric layer. A laser is used to ablate the fuse material and any protective dielectric layer that is covering the fuse material.
Traditionally, the formation of fuses in semiconductor structures, including a damascene structure, requires depositing, patterning, and etching a polysilicon or metal layer. Blowing the fuses formed from performing such steps may increase contamination because particles of the blown fuse and the protective dielectric material may be scattered to other columns/rows. Further, for the case of a damascene structure, empty trenches may result from removal of the fuse material, which may create difficult topography for any subsequent dielectric deposition and may lead to reliability problems.
SUMMARY OF THE INVENTION
According to one embodiment of the invention, a method is provided. The method includes lining, with a conductive liner, a surface of a dielectric layer. The surface defines at least two trenches separated by a platform. Each of the defined trenches includes a conductor that overlies the conductive liner and is positioned within the each of the defined trenches. The conductor is electrically coupled to the conductive liner. The method also includes covering the portion of the conductive liner overlying the platform after lining the surface. The method also includes removing any uncovered portions of the conductive liner while leaving in place the portion of the conductive liner that was covered.
Some embodiments of the invention provide numerous technical advantages. Some embodiments may benefit from some, none, or all of these advantages. For example, according to one embodiment, the fabrication of semiconductor devices requiring fuses is simplified by avoiding extra deposition steps and instead forming the fuses using an existing liner or barrier of the semiconductor structure. According to another embodiment, the blowing of the fuse is facilitated because the material used to form the fuse is relatively thin. According to another embodiment, having a thin fuse allows the blowing of the fuse using electrical current as well as laser exposure, which reduces the level of contamination, improves reliability and greatly simplifies electrical programming at test. According to another embodiment, the coverage requirement for any protective dielectric layer is reduced because of the amount of topology, such as trenches, that results from blowing fuses using laser exposure is reduced.
Other technical advantages may be readily ascertained by one of skill in the art.
REFERENCES:
patent: 6498385 (2002-12-01), Daubenspeck et al.
Brady III W. James
Garner Jacqeline J.
Lebentritt Michael S.
Owens Beth E.
Telecky , Jr. Frederick J.
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