Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2002-09-04
2004-03-30
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S429000, C438S430000, C438S435000
Reexamination Certificate
active
06713365
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to high density semiconductor devices and, more particularly, to methods of isolating semiconductor devices on a microchip.
2. Description of Related Art
Successful manufacture of high density integrated circuits, such as processors, controllers, and memories, relies upon the ability to isolate each individual device within a circuit from those surrounding it. Modem integrated circuits comprise millions of densely packed transistors, diodes, capacitors, and resistors formed on a single semiconductor substrate. Individual devices are isolated from one another to prevent phenomena such as current leakage or cross-talk between adjacent devices. Two standard methods of electrically isolating devices are local oxidation of silicon (LOCOS) and shallow trench isolation (STI).
In the LOCOS isolation process, a field oxide is grown in non-active regions of the semiconductor substrate. This isolation process has been widely used for isolating metal oxide semiconductor (MOS) devices such as NMOS, PMOS, and CMOS devices in previous generations of integrated circuits. However, LOCOS technology includes two limitations that can become increasingly pronounced as device dimensions shrink. In the LOCOS isolation process an oxide undergrowth known as a birds beak occurs at the edges of the field oxide regions, which can impose an undesirable limitation to device densities. Thus, the LOCOS isolation process may substantially restrict the maximum number of devices available in the manufacture of integrated circuits. The field oxide also extends vertically, creating a non-planar topography between the active and inactive regions. This non-planar topography may cause difficulties in later photolithographic processing such as problems resolving an image. As a result of these limitations, LOCOS technology can be ineffective for semiconductor processes involving devices dimensions, for example, below about 0.35 &mgr;m.
A process more suitable to the manufacture of ultra large scale integrated (ULSI) circuits, in which device dimensions fall below 0.35 &mgr;m, is STI In the STI process a trench is formed in a semiconductor substrate by forming protective layers and then etching through portions of those layers where isolation trenches are desired. Numerous steps are then performed to fill the trenches with an appropriate dielectric or combination of dielectrics. By etching almost vertically to form trenches having a dimension on the scale of a micron or sub-micron, valuable area can be preserved for the formation of a dense array of devices. A standard method utilized to form isolation trenches is referred to as the deposition
1
, wet etch, deposition
2
technique, in which a first trench fill layer is formed inside a trench, a wet etch is performed to remove portions of the first trench fill layer, and a second trench fill layer is formed to completely fill the trench.
STI has become the preferred method of isolation for ULSI circuits, because it requires very little area on the semiconductor substrate thereby allowing devices to be more densely distributed. Denser distributions can enable the fabrication of circuits with enhanced speed and power. STI structures also possess a relatively planar topography, which can facilitate subsequent photolithographic processing and an attenuation of errors.
Unresolved problems in the manufacture of isolation trenches, however, can still limit device densities. One problem associated with current STI techniques is the formation of air gaps or voids in the trench fill layer. Such voids can occur, for example, at or below dimensions of about 0.25 &mgr;m and depths above about 0.4 &mgr;m. These voids can adversely effect electrical characteristics of adjacent devices and can be a mechanism for device failure. Therefore, a need exists in the art to create relatively narrow and/or relatively deep trench isolation structures without the formation of voids.
SUMMARY OF THE INVENTION
The present invention addresses this need by providing methods for manufacturing isolation trenches in which the possibility or probability of forming voids or air gaps in the trenches is attenuated or eliminated. Consequently, the formation of isolation trenches in accordance with the present invention can reduce failures in adjacent devices.
The invention herein disclosed provides methods of effectively controlling the formation of voids or air gaps by performing a wet spin etch treatment between fill layers. The wet spin etch treatment can provide selectivity between the lateral etch rate and the vertical etch rate, thereby producing or approaching minimal or desirable aspect ratios.
In accordance with an aspect of the present invention, a method for making at least one isolation trench for an integrated circuit on a semiconductor substrate comprises (a) providing a semiconductor substrate having a pad oxide layer, a nitride layer, and a patterned photoresist layer, (b) removing portions of the nitride layer, pad oxide layer, and semiconductor substrate to form at least one trench; (c) removing the photoresist; (d) forming a first fill layer inside the at least one trench; (e) etching back the first fill layer with a wet spin etch; and (f) forming a second fill layer over the first fill layer. An oxide liner may be formed on the walls and base of the trench after the photoresist is removed.
According to another aspect of the invention, a method of forming at least one isolation trench comprises providing a semiconductor substrate having at least one trench disposed therein, the at least one trench having a trench sidewall and a trench base; forming a first fill layer inside the at least one trench; performing an etch process wherein portions of the first fill layer are removed from the trench sidewall at a greater rate or to a greater extent than from the trench base; and forming a second fill layer over the first fill layer.
Portions of the nitride layer, pad oxide layer, and semiconductor substrate may be removed, for example, by an anisotropic etch or an anisotropic etch followed by an isotropic etch. The first fill layer may comprise an oxide formed by HDPCVD with SiH
4
. A mixture of SiH
4
and O
2
may be implemented to form the oxide, the SiH
4
flow ranging from 50 to 100 SCCM, and the O
2
flow ranging from 80 to 150 SCCM. Deposition times may range from 10 seconds to 30 seconds. The second fill layer may also comprise an oxide formed by CVD, PECVD, or LPCVD. The formation of the second fill layer may comprise a first step of flowing 80 to 140 SCCM of SiH
4
and 130 to 200 SCCM of O
2
, followed by a second step of flowing 110 to 180 SCCM of SiH
4
and 180 to 250 SCCM of O
2
.
A dimension, such as a width, of the at least one trench may range from 0.25 to 0.18 &mgr;m. The spin speed of the wafer during the wet spin etch can be modified or tuned to create a wider top trench size and a smaller step height, thereby creating a lower aspect ratio of the resulting partially-filled trench. The wet spin etch may comprise a mixture of buffered oxide etch (BOE) and diluted hydrofluoric acid (DHF), the chemical composition ranging from a ratio of about 10:1 to about 500:1. Between 100 angstroms and 300 angstroms may be removed during the wet spin etch. During the wet spin etch, the wafer may be situated horizontally and spun horizontally, or, for example, situated vertically and spun vertically. The at least one trench may comprise a plurality of trenches.
A method in accordance with another aspect of the invention comprises (a) determining a geometrical characteristic of the isolation trench; and (b) generating a wet-spin etch recipe to be used in a deposition
1
, wet spin etch, deposition
2
trench filling sequence, wherein the wet-spin etch recipe is generated based upon the determined geometrical characteristic. The geometric characteristic may be an aspect ratio of the isolation trench. The generating of the wet-spin etch recipe may comprise selecting a spin rate, wherein greater spin rates
Chen Lee-Jen
Lin Chin-Hsiang
Isaac Stanetta
Macronix International Co. Ltd.
Niebling John F.
Stout, Uxa Buyan & Mullins, LLP
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