Semiconductor device manufacturing: process – Making passive device – Resistor
Reissue Patent
1994-09-29
2002-06-25
Picardat, Kevin (Department: 2822)
Semiconductor device manufacturing: process
Making passive device
Resistor
C438S532000, C438S625000, C438S647000
Reissue Patent
active
RE037769
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related generally to integrated circuits, and more specifically to a contact between different layers of polycrystalline silicon interconnect.
2. Description of the Prior Art
In semiconductor circuits, it is known that ohmic contacts are desirable between interconnect layers. An ohmic contact is one in which no P-N junction is formed.
When polycrystalline silicon interconnect lines having different conductivity types make contact, a P-N junction is formed. A similar junction can be formed when polycrystalline silicon having the same conductivity type, but very different doping levels (such as N
−− to N
+
) make contact. For various reasons, it is often desirable to have interconnect having different conductivity types make contact, and it would be desirable to provide an ohmic contact for such structures.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an ohmic contact between polycrystalline silicon interconnect layers having different conductivity types.
It is another object of the present invention to provide such a contact which is easily formed with a process compatible with existing process technologies.
It is a further object of the present invention to provide such a contact which is suitable for use in an SRAM structure to provide a load.
Therefore, according to the present invention, a contact structure provides electrical contact between two polycrystalline silicon interconnect layers. The lower layer has a silicide layer on its upper surface. The upper polycrystalline silicon layer can be doped with a different conductivity type, and makes the ohmic contact with the silicided region of the lower polycrystalline silicon layer.
REFERENCES:
patent: 4178674 (1979-12-01), Liu et al.
patent: 4180826 (1979-12-01), Shappir
patent: 4214917 (1980-07-01), Clark et al.
patent: 4290185 (1981-09-01), McKenny et al.
patent: 4322821 (1982-03-01), Lohstroh et al.
patent: 4367580 (1983-01-01), Guterman
patent: 4370798 (1983-02-01), Lien et al.
patent: 4398335 (1983-08-01), Lehrer
patent: 4505026 (1985-03-01), Bohr et al.
patent: 4535427 (1985-08-01), Jiang
patent: 4554729 (1985-11-01), Tanimura et al.
patent: 4560419 (1985-12-01), Bourassa et al.
patent: 4561907 (1985-12-01), Raicu
patent: 4562640 (1986-01-01), Widmann et al.
patent: 4581623 (1986-04-01), Wang
patent: 4617071 (1986-10-01), Vora
patent: 4619037 (1986-10-01), Taguchi et al.
patent: 4654824 (1987-03-01), Thomas et al.
patent: 4658378 (1987-04-01), Bourassa
patent: 4675715 (1987-06-01), Lepselter et al.
patent: 4677735 (1987-07-01), Malhi
patent: 4714685 (1987-12-01), Schubert
patent: 4792923 (1988-12-01), Nakase et al.
patent: 4804636 (1989-02-01), Groover, III et al.
patent: 4831424 (1989-05-01), Yoshida et al.
patent: 4849344 (1989-07-01), Desbiens et al.
patent: 4870033 (1989-09-01), Hotta et al.
patent: 4874719 (1989-10-01), Kurosawa
patent: 4877483 (1989-10-01), Bergemont et al.
patent: 4903096 (1990-02-01), Masuoka et al.
patent: 4907052 (1990-03-01), Takada et al.
patent: 4922455 (1990-05-01), Chinn et al.
patent: 4933735 (1990-06-01), Potash et al.
patent: 4948747 (1990-08-01), Pfiester
patent: 4950620 (1990-08-01), Harrington, III
patent: 4966864 (1990-10-01), Pfiester
patent: 4968645 (1990-11-01), Baldi et al.
patent: 5021849 (1991-06-01), Pfiester et al.
patent: 5107322 (1992-04-01), Kimura
patent: 5151376 (1992-09-01), Spinner, III
patent: 5187114 (1993-02-01), Chan et al.
patent: 5196233 (1993-03-01), Chan et al.
patent: 182610 (1986-05-01), None
patent: 58-135653 (1983-08-01), None
patent: 60-68634 (1985-04-01), None
patent: 62-98660 (1987-05-01), None
Wolf, Stanley, Silicon Processing for the VLSI Era, vol. 2, Lattice Press, Sunset Beach, Calif. (1990), Chapters 3&4.*
IEEE Trans. Electron Dev. vol. 32, No. 9, Sept. 1985, “Ion-Implanted Thin Polycrystalline High-Value Resistors for High-Density Poly-Load Static RAM Applications”, Ohzone et al.
IEEE Trans Electron Dev., vol. 40. No. 2, Feb. 1993, “Experimental Characterization of the Diode-Type Polysilicon Loads for CMOS SRAM”, Kalnitsky et al., pp. 358-363.
IEEE Trans. Electron Dev., vol. 30, No. 1, Jan. 1993, “Gigaohm-Range Polycrystalline Silicon Resistors for Microelectronic Appn”, Mohan et al., pp. 45-51.
IEEE J of Solid State Cir., vol. 18. No. 5, Oct. 1983, “A 4.5 ns Access Time 1K×4 Bit ECL RAM”, Nakubo et al., pp. 515-520.
IEEE J. of Solid State Cir, vol. 24, No. 2, Apr. 1989, “A Bipolar ECL Static RAM Using Polysilicon Diode Loaded Memory Cell”, Hwang et al., pp. 504-511.
IEEE GaAs IC Symposium, 1984, Hayashi et al., “ECL-Compatible GaAs SRAM Circuit Technology for High Performance Computer Application”, pp. 111-114.
IEEE J. of Solid State Cir, vol. 21, No. 5, Oct. 1986, “A 1.0-ns 5-Kbit ECL RAM”, Chuang et al., pp. 670-674.
Physics of Semiconductors, S.M. Sze, 1981, pp. 304-305.
Solid State Elect, vol. 30, No. 3, pp. 339-343, 1987, “Characterization of Aluminum/LPCVD Polysilicon Schottky Barrier Diodes”, Chen et al.
Solid State Elect., vol. 28 No. 12, pgs. 1255-1261 1985 “Field Enhanged Emission and Capture in Polysilicon pn Junctions”, Greve et al.
Solid State Electronics, vol. 15, pp. 1103-1106, 1972, “P-N junctions in Polycrystalline Silicon Films,” Manoliu et al.
1989 Symposium on VLSI Technology, Digest of Technical Papers, pp. 61-62, May 22-25, “A New Process Technology for a 4Mbit SRAM with Polysilicon Load Resistor Cell”, Yuzuriha et al.
Silicon Processing for the VLSI Era, vol. 2-Process Integration, pp. 84-85, 176-177, x-xv, 1986, Wolf.
Brady James
Chan Tsiu Chiu
Culver David Scott
Carlson David V.
Jorgenson Lisa K.
Picardat Kevin
STMicroelectronics Inc.
LandOfFree
Methods for fabricating memory cells and load elements does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods for fabricating memory cells and load elements, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods for fabricating memory cells and load elements will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2917912