Methods for fabricating latchup-preventing CMOS device

Details Methods for fabricating latchup-preventing CMOS device Methods for fabricating latchup-preventing CMOS device

1986-11-21

1988-08-23

Ozaki, George T.

Fishing, trapping, and vermin destroying

437 63, 437 68, H01L 21425

Patent

active

047660902

ABSTRACT:
A new CMOS device which avoids latchup while achieving a spacing between the n-channel and p-channel FETs of the device smaller than 10 .mu.m, as well as a method for fabricating the choice, is disclosed.
The inventive device, which is formed in a substrate comprising a relatively heavily doped bulk region supporting a relatively thin, moderately doped layer, includes a polysilicon-filled trench extending through a portion of the layer, between the n- and p-channel FETs of the device. The inventive device also includes a relatively heavily doped region extending from a bottom of the trench to the bulk region. The polysilicon-filled trench, in combination with both the relatively heavily doped region and bulk region, prevents latchup.

REFERENCES:
patent: 4318751 (1982-03-01), Horng
patent: 4331708 (1982-05-01), Hunter
patent: 4369565 (1983-01-01), Muramatsu
patent: 4477310 (1984-10-01), Park et al.
patent: 4519128 (1985-05-01), Chescbro et al.
patent: 4534824 (1985-08-01), Chen
patent: 4633290 (1986-12-01), Poppert et al.

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