Methods for fabricating integrated circuit devices using...

Details Methods for fabricating integrated circuit devices using... Methods for fabricating integrated circuit devices using...

2002-01-16

2003-12-16

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

With electrical circuit layout

C438S004000, C438S128000, C438S215000, C438S387000, C438S622000, C438S800000

Reexamination Certificate

active

06664140

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to integrated circuit devices and fabrication methods, and more particularly to integrated circuit devices and fabrication methods that use plasma processing.
BACKGROUND OF THE INVENTION
Plasma processing is widely used in fabricating integrated circuit devices. Plasma processing may include dry etching, thin film deposition, ashing and blanket etching. In particular, dry etching is widely used in fabricating highly integrated devices because anisotropic etching may be produced, to thereby allow submicron devices to be formed.
Unfortunately, plasma processing may also produce undesirable damage in the integrated circuit device. More particularly, since the plasma comprises a mix of charged particles, the particles may undesirably accumulate on certain surfaces. Thus, a conductive line such as a gate electrode of an integrated circuit field effect transistor may accumulate undesired charges thereon during plasma processing. The plasma charges may flow toward the edge of the conductive line in an effect known as the “antenna effect”, and thereby damage an underlying insulator. Integrated circuit field effect transistors may be particularly susceptible to this damage because the insulated gate electrode thereof generally includes a very thin gate insulating layer between the gate electrode and the surface of the integrated circuit. This gate insulator damage may degrade the properties of the field effect transistor and/or reduce the yield of the integrated circuit manufacturing process. Moreover, the degraded performance may not become apparent until after the integrated circuit is placed in the field, thereby degrading the reliability to the end user.
In order to reduce plasma processing damage, it is known to connect a junction diode to a conductive line such as a gate electrode on an integrated circuit substrate. Thus, for an NMOS transistor, it is known to add an NP diode and for a PMOS transistor it is known to add a PN diode, to thereby allow the charges generated on the conductive line during the plasma process to dissipate into the integrated circuit substrate through the junction diode. The addition of a junction diode to reduce plasma processing damage is illustrated in
FIGS. 1-4
.
FIGS. 1-3
are top and cross-sectional views of a conventional integrated circuit device that includes a diode to reduce plasma processing damage.
FIG. 2
is a cross-sectional view of
FIG. 1
taken along the line
2
-
2
′ and
FIG. 3
is a cross-sectional view of
FIG. 1
taken along the line
3
-
3
′.
Referring to
FIGS. 1-3
, a conventional integrated circuit field effect transistor, such as an NMOS transistor, includes a well
12
of first conductivity type, here p-type, in an integrated circuit substrate such as a silicon semiconductor substrate
10
. A field oxide layer
14
is formed in the integrated circuit substrate. A gate insulating layer
16
is formed on the face of the integrated circuit substrate. A gate electrode such as an L-shaped gate electrode
18
is formed. The gate electrode
18
may include sidewall spacers
20
. Spaced apart source and drain regions
22
of second conductivity type, here n-type, are formed on opposite sides of the gate electrode
18
. A second conductivity type bulk region
24
may be included in the first conductivity type well
12
. A junction diode is formed by forming a second conductivity type region
26
, here n-type, in the first conductivity type well
12
.
Continuing with the description of
FIGS. 1-3
, an interlayer insulating layer
28
is formed on the integrated circuit substrate, including on the gate electrode
18
. The interlayer insulating layer
28
includes contact holes therein that individually expose the bulk region
24
, the source/drain regions
22
, the second conductivity type region
26
of the junction diode, and the gate electrode
18
on the field oxide layer
14
. Conductive plugs such as tungsten plugs
30
are formed in the contact holes. A first metallization line
32
a
is formed on the interlayer insulating layer
28
opposite the integrated circuit substrate
10
and is connected to the gate electrode
18
and the second conductivity type region
26
of the junction diode. A plurality of second metallization lines
32
b
are formed to individually connect the bulk region
24
, the source/drain regions
22
and the second conductivity type region
26
of the junction diode via the conductive plugs
30
. A second insulating layer
34
is then formed on the interlayer insulating layer
28
including on the first and second metallization lines
32
a
and
32
b.
FIG. 4
is an equivalent circuit of the integrated circuit device of
FIGS. 1-3
. As shown in
FIG. 4
, the gate electrode G of the NMOS transistor is electrically connected to the NP junction diode by the first metallization line
32
a
(FIGS.
1
and
3
). Plasma charges that are generated during plasma processing therefore flow into the substrate through the diode. Thus, when plasma processing is performed in order to form the gate electrode, plasma charges can flow into the substrate through the junction diode, thereby reducing damage from the plasma.
Unfortunately, the use of a junction diode that is connected to a conductive line such as a gate electrode may not prevent all plasma processing-induced damage to the underlying insulator. As the integration density of integrated circuit devices continues to increase, and the thickness of the gate insulator continues to decrease, this remaining plasma processing damage may continue to impact the performance, yield and/or reliability of the integrated circuit devices.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved integrated circuit devices and fabrication methods therefor.
It is another object of the present invention to provide integrated circuits and fabrication methods that can reduce damage during plasma processing.
It is another object of the present invention to provide integrated circuit devices and fabrication methods that can reduce damage during plasma processing compared to devices that include a diode connected to a conductive line.
These and other objects are provided according to the present invention by an integrated circuit that includes first and second diodes that are electrically connected to a conductive line in antiparallel, to dissipate both positive and negative charges on the conductive line during plasma processing. The integrated circuit also includes means for disconnecting one of the first and second diodes from the conductive line after the plasma processing, to thereby allow conduction of one of positive and negative charge on the conductive line after the plasma processing.
It has been found, according to the present invention, that although the use of a single diode may allow one of the positive and negative charges to dissipate into the substrate, the other of the positive and negative charges does not dissipate into the substrate, because the diode prevents flow of the other of the positive and negative charges. For example, for an NP diode, negative charges can flow freely toward the substrate from the conductive line, but positive charges do not flow. Thus, the positive charges can damage the underlying insulating layer. The same phenomenon may take place when a PN diode is connected to the gate electrode of a PMOS transistor, except that positive charges flow into the substrate but negative charges are trapped.
In sharp contrast, the present invention allows both positive and negative charges to flow from the conductive line into the substrate during plasma processing. After plasma processing, one of the first and second diodes is disconnected so that only one type of charge, such as negative charge, is conducted on the conductive line during normal operation of the integrated circuit. Thus, normal operation of the integrated circuit need not be degraded.
Accordingly, integrated circuits are fabricated according to the present invention by forming a conductive line

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