Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Patent
1995-12-28
1998-08-11
Carroll, J.
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
257 50, 438131, 438467, 438600, H01L 2900
Patent
active
057930945
ABSTRACT:
A method for substantially reducing variations in a programming voltage of an anti-fuse structure formed on an integrated circuit wafer. The anti-fuse structure has a metal-one layer, an anti-fuse layer disposed above the metal-one layer, a oxide layer disposed above the anti-fuse layer, and a via hole in the oxide layer through to the anti-fuse layer for receiving a deposition of a metal-two material. The method includes the step of rendering a selected anti-fuse area susceptible to fuse link formation by reducing a resistivity of the selected anti-fuse area to diffusion of atoms from one of the metal-one layer and the metal-two layer when a programming voltage is applied between the metal one layer and the metal two layer. The selected anti-fuse area is located in the anti-fuse layer and substantially adjacent to and outside of an anti-fuse area directly below the via hole. The method further includes the step of depositing the metal-two material into the via hole.
REFERENCES:
patent: 4174521 (1979-11-01), Neale
patent: 4420766 (1983-12-01), Kasten
patent: 4441167 (1984-04-01), Principi
patent: 4538167 (1985-08-01), Yoshino et al.
patent: 4569120 (1986-02-01), Stacy et al.
patent: 5070384 (1991-12-01), McCollum et al.
patent: 5095362 (1992-03-01), Roesner
patent: 5106773 (1992-04-01), Chen et al.
patent: 5120769 (1992-06-01), Boardman et al.
patent: 5191241 (1993-03-01), McCollum et al.
patent: 5210598 (1993-05-01), Nakazaki et al.
patent: 5233206 (1993-08-01), Lee et al.
patent: 5248632 (1993-09-01), Tung et al.
patent: 5258891 (1993-11-01), Sako
patent: 5266829 (1993-11-01), Hamdy et al.
patent: 5272666 (1993-12-01), Tsang et al.
patent: 5290734 (1994-03-01), Boardman et al.
patent: 5293133 (1994-03-01), Birkner et al.
patent: 5298784 (1994-03-01), Gambino et al.
patent: 5300456 (1994-04-01), Tigelaar et al.
patent: 5308795 (1994-05-01), Hawley et al.
patent: 5311039 (1994-05-01), Kimura et al.
patent: 5328868 (1994-07-01), Conti et al.
patent: 5373169 (1994-12-01), McCollum et al.
patent: 5381035 (1995-01-01), Chen et al.
patent: 5404029 (1995-04-01), Husher et al.
patent: 5427979 (1995-06-01), Chang
patent: 5434432 (1995-07-01), Spratt et al.
patent: 5464790 (1995-11-01), Hawley
patent: 5489796 (1996-02-01), Harward
patent: 5493144 (1996-02-01), Bryant et al.
patent: 5493146 (1996-02-01), Pramanik et al.
patent: 5502315 (1996-03-01), Chuca et al.
patent: 5557136 (1996-09-01), Gordon et al.
patent: 5593920 (1997-01-01), Haslam et al.
Unknown, "Developments in non-volatile FPGAs", Electronic Engineering, Apr., 1993.
K.E. Gordon and R.J. Wong, "Conducting Filament of the Programmed Metal Electrode Amorphous Silicon Antifuse", QuickLogic Corp., Santa Clara, CA, 1993 IEEE, International Electron Devices Meeting, Dec. 5-8, 1993, Washington, DC.
Han Yu-Pin
Loh Ying-Tsong
Parmantie Walter D.
Sanchez Ivan
Carroll J.
VLSI Technology Inc.
LandOfFree
Methods for fabricating anti-fuse structures does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods for fabricating anti-fuse structures, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods for fabricating anti-fuse structures will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-391847