Methods for fabricating a multi-bit storage cell

Details Methods for fabricating a multi-bit storage cell Methods for fabricating a multi-bit storage cell

1995-03-27

1996-06-25

Nguyen, Tuan H.

Fishing, trapping, and vermin destroying

437 47, 437 60, 437919, 148DIG14, H01L 2170

Patent

active

055299458

ABSTRACT:
A method is disclosed for fabricating a multi-bit storage location at the face of a layer of semiconductor. First and second conductive gates are formed insulatively spaced from the semiconductor layer and spaced from each other by an area of the semiconductor layer, at least a portion of this area comprising a first capacitor area laterally adjacent the first gate. A doped source/drain of a second conductivity type is formed in the layer adjacent the first gate and spaced from the first capacitor area. A first capacitor conductor is formed insulatively adjacent the first capacitor area and extends laterally from the first gate. A second capacitor conductor is formed insulatively adjacent a second capacitor area laterally adjacent the second gate.

REFERENCES:
patent: 4710896 (1987-12-01), Nagami
patent: 5341326 (1994-08-01), Takase et al.
patent: 5359566 (1994-10-01), Furuyama
patent: 5369612 (1994-11-01), Furuyama
patent: 5372965 (1994-12-01), Ryou
patent: 5422295 (1995-06-01), Choi et al.
patent: 5441908 (1995-08-01), Lee et al.
patent: 5447878 (1995-09-01), Park et al.

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