Methods for fabricating a dual-gated semiconductor-on-insulator

Details Methods for fabricating a dual-gated semiconductor-on-insulator Methods for fabricating a dual-gated semiconductor-on-insulator

1991-12-27

1993-12-28

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 44, 437 89, 437915, H01L 21265

Patent

active

052739210

ABSTRACT:
A method for forming a dual-gated Semiconductor-On-Insulator (SOI) field effect transistor for integrated circuits includes the formation of a gate/oxide/channel/oxide/gate stack on top of an insulating layer. The process begins with the formation of a first gate electrode and first oxide layer on an insulating layer. Then, a seed hole in the insulating layer is formed exposing the underlying substrate. This is followed by the epitaxial lateral overgrowth (ELO) of monocrystalline silicon, for example, from the seed hole to on top of the first oxide layer. This monocrystalline layer forms the device channel. A second oxide and second gate electrode layer are then grown and deposited, respectively. Subsequent etch steps employing sidewall spacers are then employed to form a multilayered stack having self-aligned first and second gate electrodes. Sidewall seed holes are then used to epitaxially grow monocrystalline source and drain regions from the channel. In-situ doping can be provided to form a lightly doped source (LDS) and drain (LDD) structure with vertically displaced source and drain contacts.

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