Methods for ESD protection

Electrical connectors – Preformed panel circuit arrangement – e.g. – pcb – icm – dip,... – Within distinct housing spaced from panel circuit arrangement

Reexamination Certificate

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Reexamination Certificate

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07416419

ABSTRACT:
A Universal Serial Bus flash memory unit having an electrically conductive housing includes a spring that provides an electrically conductive, low-resistance pathway between the housing and the metal shell of the Universal Serial Bus connector so that electrostatic charge can directly discharge from the housing to the metal shell instead of discharging through electronic components within the housing.

REFERENCES:
patent: 5627729 (1997-05-01), Oldendorf et al.
patent: 5887145 (1999-03-01), Harari et al.
patent: 6385677 (2002-05-01), Yao
patent: 6513720 (2003-02-01), Armstrong
patent: 6561421 (2003-05-01), Yu
patent: 6722924 (2004-04-01), Zhou et al.
patent: 6733329 (2004-05-01), Yang
patent: 6792487 (2004-09-01), Kao
patent: 6808400 (2004-10-01), Tu
patent: 6890188 (2005-05-01), Le
patent: 7118414 (2006-10-01), Spears et al.
patent: 7153148 (2006-12-01), Chen et al.
patent: 7252518 (2007-08-01), Ni
patent: 2001/0036524 (2001-11-01), Anderson
patent: 2003/0028797 (2003-02-01), Long et al.
patent: 2003/0212848 (2003-11-01), Liu et al.
patent: 2004/0040871 (2004-03-01), Kakinoki et al.
patent: 2005/0139683 (2005-06-01), Yi
patent: 2005/0181645 (2005-08-01), Ni et al.
patent: 2005/0230484 (2005-10-01), Cuellar et al.
patent: 2006/0038023 (2006-02-01), Brewer et al.
patent: 2006/0192004 (2006-08-01), Elazar et al.
patent: 2007/0015407 (2007-01-01), Loftus
patent: 2007/0184685 (2007-08-01), Hsueh et al.
patent: 2003-54676 (2003-02-01), None
USPTO, “Office Action” mailed in U.S. Appl. No. 11/465,045 on Aug. 23, 2007, 10 pages.
Patricio Collantes, Jr. et al., “Connector With ESD Protection,” U.S. Appl. No. 11/465,045, filed Aug. 16, 2006, 13 pages.
Office Action dated Mar. 14, 2008, U.S. Appl. No. 11/465,405, filed Aug. 16, 2006.
Universal Serial Bus Specification Revision 2.0, Chapter 6—Mechanical, p. 85-118, no date.

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