Methods for determining on-chip interconnect process parameters

Details Methods for determining on-chip interconnect process parameters Methods for determining on-chip interconnect process parameters

1997-09-25

2000-05-02

Niebling, John F.

Semiconductor device manufacturing: process

With measuring or testing

Packaging or treatment of packaged semiconductor

438 14, 364490, H01L 2166, G01R 3126

Patent

active

060571713

ABSTRACT:
A method provides estimations of physical interconnect process parameter values in a process for manufacturing integrated circuits. The method includes fabricating test structures each providing a value of a measurable quantity corresponding to a value within a range of values of the physical interconnect process parameters. In some embodiments, the measured value is used to derive the values of the physical interconnect process parameters, either by a numerical method using a field solver, or by a closed-form solution. The values of physical interconnect process parameters involving physical dimensions are also obtained by measuring photomicrographs obtained using a scanning electron microscope from cross sections of test structures. In some embodiments, a family of test structures corresponding to a range of conductor widths and a range of spacings between conductors are measured.

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"Nondestructive Multilevel Interconnect Parameter Characterization for High-Performance Manufacturable VLSI Technologies", Ke-Jeng Chang, et al., 1993 Symposium VLSI Technology, 1993, pp. 135-136.
"Effect of Fine-Line Density and Pitch on Interconnect ILD Thickness Variation in Oxide CMP Processes", Divecha et al., CMP-MIC Conference, pp. 29-36, Feb. 1997.

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