Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2002-08-29
2003-06-24
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
C438S003000
Reexamination Certificate
active
06582977
ABSTRACT:
FIELD OF INVENTION
The present invention relates generally to the art of semiconductor devices and more particularly to methods for determining process related charging during semiconductor processing operations.
BACKGROUND OF THE INVENTION
In the course of manufacturing semiconductor devices, certain processing steps involve the use of electrically charged plasma. Ion implantation, plasma etching, plasma enhanced deposition processes and other charged processing operations may damage semiconductor wafers, and the devices and circuits formed therein. The plasma in such processes includes charged particles, some of which may accumulate on the wafer surface through antenna charging. For example, in back-end-of-line (BEOL) interconnect processing, inter layer dielectric (ILD) material is often deposited using plasma enhanced chemical vapor deposition (PECVD) and etched using plasma based reactive ion etching (RIE).
During interconnect processing, moreover, one or more patterned metal layers are formed over and between ILD layers to electrically connect electrical devices formed on or in the substrate, such as transistors, memory cells, and the like. The electrical terminals of these devices, such as gates, and source/drain regions, are thus often electrically connected to conductive features directly exposed to these back end processes, which operate as charge gathering antennas. As a result, charge accumulating on exposed conductive features may be discharged through the electrical devices to the substrate, sometimes causing damage and/or performance degradation in the electrical devices. Of particular interest is damage or degradation of the gate oxide layer in MOS type transistors fabricated in a wafer.
Various devices have thusfar been developed to measure the resulting voltage potential (or a current flow) between a charge collection area on the surface of the semiconductor device wafer and the substrate during processing operations or steps. Such devices include monitors or sensors located proximate the wafer workpieces during process steps of interest, which provide sensor signals to control systems or user interface devices. The actual charging of the semiconductor wafer is then inferred from the sensor signal. Charge monitoring (CHARM) wafers have been extensively employed in characterizing process related charging levels, which can be inserted into a process chamber to record the charging levels encountered therein. The CHARM test wafers include a series of electrically erasable programmable read only memory (EEPROM) cell charge sensors or detectors connected between the substrate and conductive antenna pads on the CHARM wafer surface. After the process, the status or data of the various EEPROM sensors is measured, and the results are evaluated using commercially available software tools.
Other process charging measurement devices have been developed, which are formed directly in the wafer workpieces or in dedicated test wafers. These in-situ process charging sensors typically consist of dedicated memory cells, such as one or more EEPROM cells formed in the production wafer. For example, one or more such EEPROM memory cells having a stacked gate MOS type transistor operating as voltage or current sensor may be formed in the production wafers, typically during back end interconnect processing. The memory cell type sensor devices are typically fabricated in peripheral areas of the wafer, such as in scribe regions between device dies on a wafer. The status of these in-situ memory cell sensors can then be interrogated before and after a process of interest to ascertain whether process related charging exceeded a threshold value associated with the cell. In this approach, a charge collection electrode is formed on the top of the wafer, and is connected to the control gate of a stacked gate MOS type transistor (EEPROM cell) to collect process related charge during processing, which in turn affects the transistor gate.
As process charge is collected at the wafer surface, the transistor based memory cell measures the resulting voltage potential between the charge collection electrode and the wafer substrate. The voltage potential in the wafer, in turn changes the threshold voltage Vt of the memory cell, and hence the threshold voltage Vt thereof can be measured before and after a plasma related processing step. A comparison of the threshold voltage measurements is then used to estimate the process charging associated with the processing step. A first or initial threshold voltage is programmed prior to exposing the wafer to a plasma related process, typically by probing the wafer and providing a known programming signal to the transistor via the charge collection electrode. At this point, the actual initial threshold voltage is sometimes measured or verified, prior to performing wafer processing steps involving potential wafer charging.
After the processing step or steps of interest, the EEPROM transistor is probed and a second or final threshold voltage is measured. Once the initial and final threshold voltages are determined, the surface potential related to the process can be estimated using a calibration curve or plot of threshold voltage shift versus gate voltage for the EEPROM transistor. In this regard, the estimated gate voltage represents the voltage potential between the charge collection electrode at the wafer surface and the wafer substrate. Where a resistance of known value is provided between the charge collection electrode and the substrate, then the process related current can be determined according to the gate voltage and the known resistance value. In this fashion, EEPROM transistor-based charge detection devices can be used to estimate the charging associated with a particular processing step.
However, EEPROM memory cell type charging sensors, including CHARM test wafers and in-situ EEPROM memory cell sensors suffer from limits in the range of detectable voltages. Such devices, for example, are generally limited to detection of process charging voltages between about −25 and +30 volts. Consequently, these EEPROM type monitor devices are unable to quantify or measure process related potentials above this range. Furthermore, the estimation of charging voltage values typically does not correlate to potential gate oxide damage or degradation in production wafers. In this regard, CHARM wafers in particular, are typically not manufactured according to a particular process flow of interest to a semiconductor manufacturer. Thus, the results obtained therefrom may not indicate potential problems in actual production wafers, or may provide false indications where gate oxide layers and other features of production devices may be unharmed by a process step or steps. Moreover, CHARM type test wafers are not suitable for all process operations. For example, these cannot be used to ascertain charging in deposition processes.
In addition, the threshold voltage of the EEPROM cell type detectors is sensitive to ultra-violet (UV) radiation. As a result, the threshold voltage shift represents both process related charging and exposure of the wafer to UV sources during processing. Thus, it may be difficult or impossible to differentiate between the two in order to accurately quantify the charging in the manufacturing process. The fabrication of in-situ EEPROM memory cell sensors, moreover, is relatively complex, requiring the formation in the wafer of the source, drain, and gate structures of the MOS type transistor, thereby making the manufacturing process more difficult. Furthermore, the above conventional test devices and techniques require multiple steps to pre-program and verify the EEPROM based test devices to a known initial threshold voltage before processing, and to measure the resulting threshold voltage after processing. Thus, there is a need for improved techniques by which the adverse effects of process related charging can be determined or monitored, without the UV sensitivity and voltage range limitations associated with prior in-situ and other charging
Krishnan Anand
Rodriguez John
Brady III W. James
Garner Jacqueline J.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tsai Jey
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