Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Pcb – mcm design
Reexamination Certificate
2011-03-29
2011-03-29
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Pcb, mcm design
C716S103000, C716S118000, C716S119000
Reexamination Certificate
active
07917885
ABSTRACT:
A high-level logic description is developed based on a non-primitive-based standard cell library. The logic description is synthesized into a netlist that includes references to the non-primitive-based standard cell library. A logic function for each standard cell in the netlist is determined and mapped into a set of primitive logic cells to create a primitive constructed version of each referenced standard cell. The set of primitive logic cells is defined for integration within a base array. The primitive constructed version of each referenced standard cell is included within a primitive-based cell library. The primitive-based cell library is used to place and route the netlist for the logic design for integration within the base array. The logic design is then integrated within the base array.
REFERENCES:
patent: 4197555 (1980-04-01), Uehara et al.
patent: 5378649 (1995-01-01), Huang
patent: 5581098 (1996-12-01), Chang
patent: 5682323 (1997-10-01), Pasch et al.
patent: 5684733 (1997-11-01), Wu et al.
patent: 5825203 (1998-10-01), Kusunoki et al.
patent: 5841663 (1998-11-01), Sharma et al.
patent: 5847421 (1998-12-01), Yamaguchi
patent: 5898194 (1999-04-01), Gheewala
patent: 5908827 (1999-06-01), Sirna
patent: 5923059 (1999-07-01), Gheewala
patent: 5935763 (1999-08-01), Caterer et al.
patent: 5977305 (1999-11-01), Wigler et al.
patent: 6100025 (2000-08-01), Wigler et al.
patent: 6174742 (2001-01-01), Sudhindranath et al.
patent: 6182272 (2001-01-01), Andreev et al.
patent: 6194252 (2001-02-01), Yamaguchi
patent: 6194912 (2001-02-01), Or-Bach
patent: 6240542 (2001-05-01), Kapur
patent: 6255600 (2001-07-01), Schaper
patent: 6260177 (2001-07-01), Lee et al.
patent: 6275973 (2001-08-01), Wein
patent: 6331733 (2001-12-01), Or-Bach et al.
patent: 6338972 (2002-01-01), Sudhindranath et al.
patent: 6416907 (2002-07-01), Winder et al.
patent: 6425117 (2002-07-01), Pasch et al.
patent: 6476493 (2002-11-01), Or-Bach et al.
patent: 6480989 (2002-11-01), Chan et al.
patent: 6505327 (2003-01-01), Lin
patent: 6525350 (2003-02-01), Kinoshita et al.
patent: 6571140 (2003-05-01), Wewalaarachchi
patent: 6574786 (2003-06-01), Pohlenz et al.
patent: 6590289 (2003-07-01), Shively
patent: 6591207 (2003-07-01), Naya et al.
patent: 6620561 (2003-09-01), Winder et al.
patent: 6661041 (2003-12-01), Keeth
patent: 6691297 (2004-02-01), Misaka et al.
patent: 6714903 (2004-03-01), Chu et al.
patent: 6737199 (2004-05-01), Hsieh
patent: 6745372 (2004-06-01), Cote et al.
patent: 6792593 (2004-09-01), Takashima et al.
patent: 6795952 (2004-09-01), Stine et al.
patent: 6807663 (2004-10-01), Cote et al.
patent: 6819136 (2004-11-01), Or-Bach
patent: 6834375 (2004-12-01), Stine et al.
patent: 6850854 (2005-02-01), Naya et al.
patent: 6854100 (2005-02-01), Chuang et al.
patent: 6877144 (2005-04-01), Rittman et al.
patent: 6884712 (2005-04-01), Yelehanka et al.
patent: 6904582 (2005-06-01), Rittman et al.
patent: 6928635 (2005-08-01), Pramanik et al.
patent: 6931617 (2005-08-01), Sanie et al.
patent: 6953956 (2005-10-01), Or-Bach et al.
patent: 6978437 (2005-12-01), Rittman et al.
patent: 6992925 (2006-01-01), Peng
patent: 7028285 (2006-04-01), Cote et al.
patent: 7041568 (2006-05-01), Goldbach et al.
patent: 7064068 (2006-06-01), Chou et al.
patent: 7093228 (2006-08-01), Andreev et al.
patent: 7103870 (2006-09-01), Misaka et al.
patent: 7120882 (2006-10-01), Kotani et al.
patent: 7137092 (2006-11-01), Maeda
patent: 7149999 (2006-12-01), Kahng et al.
patent: 7155689 (2006-12-01), Pierrat
patent: 7278118 (2007-10-01), Pileggi et al.
patent: 7343581 (2008-03-01), Becker
patent: 2004/0145028 (2004-07-01), Matsumoto et al.
patent: 2004/0161878 (2004-08-01), Or-Bach et al.
patent: 2004/0243966 (2004-12-01), Dellinger
patent: 2005/0055828 (2005-03-01), Wang et al.
patent: 2005/0101112 (2005-05-01), Rueckes et al.
patent: 2005/0189614 (2005-09-01), Ihme et al.
patent: 2005/0224982 (2005-10-01), Kemerling et al.
patent: 2006/0121715 (2006-06-01), Chang et al.
patent: 2006/0151810 (2006-07-01), Ohshige
patent: 2006/0223302 (2006-10-01), Chang et al.
patent: H06-188312 (1994-07-01), None
patent: WO 2006/014849 (2006-02-01), None
Koorapaty et al., “Exploring Logic Block Granularity for Regular Fabrics”, 2004, IEEE.
U.S. Appl. No. 60/625,342, filed May 25, 2006, Pileggi et al.
Wang, J. et al., Statndard Cell Layout with Regular Contact Placement, IEEE Trans. on Semicon. Mfg., vol. 17, No. 3, Aug. 2004.
Kang, S.M., Metal-Metal Matrix (M3) for High-Speed MOS VLSI Layout, IEEE Trans. on CAD, vol. CAD-6, No. 5, Sep. 1987.
Liebmann, L. W., Layout Impact of Resolution Enhancement Techniques: Impediment or Opportunity?, International Symposium on Physical Design, 2003.
Jhaveri, T. et al., Maximization of Layout Printability/Manufacturability by Extreme Layout Regularity, Proc. of the SPIE, Apr. 2006.
ACAR, et al., “A Linear-Centric Simulation Framework for Parametric Fluctuations”, 2002, IEEE, Carnegie Mellon University USA, pp. 1-8.
Amazawa, et al., “Fully Planarized Four-Level Interconnection with Stacked VLAS Using CMP of Selective CVD-A1 and Insulator and its Application to Quarter Micron Gate Array LSIs”, 1995, IEEE, Japan, pp. 473-476.
Burkhardt, et al., “Dark Field Double Dipole Lithography (DDL) for Back-End-Of-Line Processes”, 2007, SPIE Proceeding Series, vol. 6520; 65200K.
Capetti, et al., “Sub k1=0.25 Lithography with Double Patterning Technique for 45nm Technology Node Flash Memory Devices at λ=193nm”, 2007, SPIE Proceeding Series, vol. 6520; 65202K.
Chandra, et al., “An Interconnect Channel Design Methodology for High Performance Integrated Circuits”, 2004, IEEE, Carnegie Mellon University, pp. 1-6.
Cheng, et al., “Feasibility Study of Splitting Pitch Technology on 45nm Contact Paterning with 0.93 NA”, 2007, SPIE Proceeding Series, vol. 6520; 65202N.
Chow, et al., “The Design of a SRAM-Based Field-Programmable Gate Array—Part II: Circuit Design and Layout”, 1999, IEEE, vol. 7 #3 pp. 321-330.
DeVor, et al., “Statistical Quality Design and Control”, 1992, Macmillan Publishing Company, pp. 264-267.
Dusa, et al. “Pitch Doubling Through Dual Patterning Lithography Challenges in Integration and Litho Budgets”, 2007, SPIE Proceeding Series, vol. 6520; 65200G.
El-Gamal, “Fast, Cheap and Under Control: The Next Implementation Fabric”, Jun. 2-6, 2003, ACM Press, pp. 354-355.
Frankel, “Quantum State Control Interference Lithography and Trim Double Patterning for 32-16nm Lithography”, 2007, SPIE Proceeding Series, vol. 6520; 65202L.
Hayashida, et al., “Manufactuable Local Interconnect technology Fully Compatible with Titanium Salicide Process”, Jun. 11-12, 1991, VMIC Conference.
Heng, et al., “A VLSI Artwork Legalization Technique Base on a New Criterion of Minimum Layout Perturbation”, 1997, ACM Press, pp. 116-121.
Hu, et al., “Synthesis and Placemant Flow for Gain-Based Programmable Regular Fabrics”, Apr. 6-9, 2003, ACM Press, pp. 197-203.
Hutton, et al., “A Methodology for FPGA to Structured-ASIC Synthesis and Verification”, 2006, EDAA, pp. 64-69.
Jayakumar, et al., “A Metal and VIA Maskset Programmable VLSI Design Methodology using PLAs”, 2004, IEEE, pp. 590-594.
Kheterpal, et al., “Routing Architecture Exploration for Regular Fabrics”, DAC, Jun. 7-11, 2004, ACM Press, pp. 204-207.
Kheterpal, et al., “Design Methodolgy for IC Manufactrability Based on Regular Logic-Bricks”, DAC, Jun. 13-17, 2005, IEEE/AMC, vol. 6520.
Kim, et al., “Issues and Challenges of Double Patterning Lithography in DRAM”, 2007, SPIE Proceeding Series, vol. 6520; 65200H.
Kim, et al., “Double Exposure Using 193nm Negative Tone Photoresist”, 2007, SPIE Proceeding Series, vol. 6520; 65202M.
Koorapaty, et al., “Exploring Logic Block Granularity for Regular Fabrics”, 2004, IEEE, pp. 1-6.
Li, et al., “A Linear-Centric Modeling Approach to H
Martine & Penilla & Gencarella LLP
Tela Innovations, Inc.
Whitmore Stacy A
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