Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2007-04-27
2009-02-17
Phung, Anh (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185030
Reexamination Certificate
active
07492636
ABSTRACT:
Methods are described for double-side-biasing of a NAND memory array device comprising a plurality of charge trapping memory cells for programming and erasing the NAND memory array device. A double-side-biasing method applies a bias voltage simultaneously on a first junction (a source region) and a second junction (a drain region) so that a left bit and a right bit in a charge trapping memory cell can be programmed in parallel or erased in parallel. Random (or selective) bit program and random (or selective) bit erase can be achieved by using a double-side-biasing method on a NAND memory array device for both data and code application. A first type of double-side-biasing method is to program the NAND array with a double-side-bias electron injection. A second type of double-side-biasing method is to erase the NAND array with a double-side-bias hole injection.
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Haynes Beffel & Wolfeld LLP
Macronix International Co. Ltd.
Phung Anh
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