Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2004-07-02
2009-06-30
Bullock, Jr., Lewis A (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S403000, C708S409000
Reexamination Certificate
active
07555511
ABSTRACT:
A method for the generation of addresses of successive pairs of input data values of stages of a Fast Fourier Transform calculation stored contiguously in a memory includes initializing at most once per stage a first base address pointer to an address of a first input data value of an initial butterfly calculation of the stage and a second base address pointer to an address of a second input data value of the initial butterfly calculation, and initializing at most once per stage a first constant and a second constant. Pairs of input data values of successive butterfly calculations in the stage are then addressed using the first base address pointer, the second base address pointer, the first constant and the second constant.
REFERENCES:
patent: 3673399 (1972-06-01), Hancke et al.
patent: 3871577 (1975-03-01), Avellar et al.
patent: 4612626 (1986-09-01), Marchant
patent: 5091875 (1992-02-01), Wong et al.
patent: 6760741 (2004-07-01), Vinitzky
patent: 0209446 (1987-01-01), None
Bullock, Jr. Lewis A
Ceva D.S.P. Ltd.
Pearl Cohen Zedek Latzer LLP
Yaary Michael
LandOfFree
Methods for addressing input data values of a Fast Fourier... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods for addressing input data values of a Fast Fourier..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods for addressing input data values of a Fast Fourier... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4078496