Methods for accelerated erase operations in non-volatile...

Details Methods for accelerated erase operations in non-volatile... Methods for accelerated erase operations in non-volatile...

2007-04-03

2007-04-03

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185220, C365S185230

Reexamination Certificate

active

11247839

ABSTRACT:
Memory cells in a memory cell array are erased using an erase operation followed by a post-program operation. In the erase operation, an erase voltage is applied to a plurality of memory cells of the memory cell array. In the post program operation, a program voltage is simultaneously applied to at least two word lines coupled to ones of the plurality of erased memory cells of the memory cell array. Related devices are also discussed.

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Notice to File a Response/Amendment to the Examination Report corresponding to Korean Patent Application No. 10-2004-0095242 mailed Mar. 9, 2006.
Notice to Submit a Response/Amendment to the Examination Report for Korean Patent Application No. 10-2004-0103528 mailed on May 29, 2006.

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