Methods and systems for reducing the threshold voltage...

Details Methods and systems for reducing the threshold voltage... Methods and systems for reducing the threshold voltage...

2007-01-30

2007-01-30

Phung, Anh (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185220, C365S185180

Reexamination Certificate

active

11193391

ABSTRACT:
A method is provided for erasing a memory device including a number of memory cells, the memory cells including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes erasing a group of memory cells to lower a maximum threshold voltage of the group of memory cells below a first predetermined level. The group of memory cells is soft-programmed to raise a minimum threshold voltage of the group of memory cells above a second predetermined level. The group of memory cells is erased, following soft-programming, resulting in a reduced threshold voltage distribution associated with the group of memory cells.

REFERENCES:
patent: 6172909 (2001-01-01), Haddad et al.
patent: 6208560 (2001-03-01), Tanaka et al.
patent: 6252803 (2001-06-01), Fastow et al.
patent: 6381177 (2002-04-01), De Sandre et al.
patent: 6483752 (2002-11-01), Hirano
patent: 6493266 (2002-12-01), Yachareni et al.

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