Methods and systems for reducing erase times in flash memory...

Details Methods and systems for reducing erase times in flash memory... Methods and systems for reducing erase times in flash memory...

2006-07-18

2006-07-18

Tran, Michael (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185240

Reexamination Certificate

active

07079424

ABSTRACT:
A method is provided for erasing a memory cell having a substrate, a control gate, a floating gate, a source region and a drain region. The method includes pre-programming the memory cell to raise a threshold voltage of the memory cell to a first predetermined level, wherein pre-programming the memory cell does not include a verification process for ensuring that the threshold voltage of the memory cell has been raised to the first predetermined level. The memory cell may be erased to lower the threshold voltage of the memory cell to a second predetermined level.

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