Static information storage and retrieval – Read only systems – Fusible
Reexamination Certificate
2003-01-31
2004-09-28
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read only systems
Fusible
C365S225700, C365S100000
Reexamination Certificate
active
06798684
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to semiconductor fuses and systems and methods for programming semiconductor fuses.
2. Background Art
In the field of data storage, there are two main types of storage elements. The first type is volatile memory that has the information stored in a particular storage element, and the information is lost the instant the power is removed from a circuit. The second type is a nonvolatile storage element, in which the information is preserved even with the power removed. In regards to the nonvolatile storage elements, some designs allow multiple programming, while other designs allow one-time programming. Typically, the manufacturing techniques used to form nonvolatile memories are quite different from a standard logic process. The non-volatile memory manufacturing techniques increase the complexity and chip size.
Complimentary Metal Oxide Semiconductor (CMOS) technology is the integration of both NMOS and PMOS transistors on a silicon substrate (collectively know as MOS field effect transistors, or MOSFETs). The NMOS transistor consists of a N-type doped polysilicon gate, a channel conduction region, and source/drain regions formed by diffusion of N-type dopants in the silicon substrate. The channel region separates the source from the drain in the lateral direction, whereas a layer of dielectric material that prevents electrical current flow separates the polysilicon gate from the channel. Similarly, the architecture is the same for the PMOS transistor, except a P-type dopant is used.
The dielectric material separating the polysilicon gate from the channel region, henceforth referred to as the gate oxide, usually consists of the thermally grown silicon dioxide (SiO
2
) material that leaks very little current through a mechanism, which is called Fowler-Nordheim tunneling under voltage stress. Thin oxides that allow direct tunneling current behave differently than thicker oxides, which exhibit Fowler-Nordheim tunneling.
Conventional semiconductor fuses are capable of being programmed through application of a large current source to its poly-silicon layer. Such application of current causes the poly-silicon layer of the fuse to melt. Molten poly-silicon agglomerates towards both ends of the fuse. One of the disadvantages of this method is that the programmed fuse is prone to contamination through the passivation window opening.
Furthermore, the need for high voltages to be internally generated to create such high currents can impact reliability of the programmed fuse and integrity of underlying oxide layers in sub-micron CMOS processing, which cannot tolerate high programming voltages. Due to this reliability hazard, the unpredictability of post-programming resistance of the fuse also increases.
Therefore, there is a need for methods and systems that are capable of providing a reliable non-volatile one-time programming memory element. One-time programmable memory element should be compatible with sub-micron CMOS processing and provide predictable post programming resistance in the fuse.
BRIEF SUMMARY OF THE INVENTION
The present invention is directed to methods and systems for evaluating one-time programmable memory cells. A threshold current is applied to a resistive circuit, thereby generating a threshold voltage. A read current is applied to a first memory cell, thereby generating a memory cell voltage. The memory cell voltage is compared to the threshold voltage, thereby determining the state of the memory cell. In a further embodiment of the invention, a second threshold voltage is generated and compared the memory cell voltage, thereby verifying the state of the memory cell. The threshold current is optionally a substantial replica of said read current. The threshold current is optionally a proportional substantial replica of said read current. In an embodiment, the resistive circuit includes a second memory cell, which can be programmed or unprogrammed. The second memory cell is optionally arranged to average the memory cell resistance.
Further embodiments, features, and advantages of the present inventions, as well as the structure and operation of the various embodiments of the present invention, are described in detail below with reference to the accompanying drawings.
REFERENCES:
patent: 5572458 (1996-11-01), Smith et al.
patent: 5828604 (1998-10-01), Kawai et al.
Brooks Todd L.
Ito Akira
Low Khim L.
Woo Agnes
Broadcom Corporation
Le Vu A.
Sterne Kessler Goldstein & Fox P.L.L.C.
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