Data processing: software development – installation – and managem – Software program development tool – Translation of code
Reexamination Certificate
2004-12-30
2010-06-29
Zhen, Wei Y (Department: 2191)
Data processing: software development, installation, and managem
Software program development tool
Translation of code
C717S140000, C717S141000, C717S160000, C717S161000, C712S212000
Reexamination Certificate
active
07747993
ABSTRACT:
A method of ordering instructions. The method can include placing a first instruction that consumes a value of an object before a second instruction that produces the value of the object such that the first instruction is processed before the second instruction and a physical location is allocated to the value of the object upon processing the first instruction.
REFERENCES:
patent: 5161216 (1992-11-01), Reps et al.
patent: 5367651 (1994-11-01), Smith et al.
patent: 5655122 (1997-08-01), Wu
patent: 5699537 (1997-12-01), Sharangpani et al.
patent: 5724565 (1998-03-01), Dubey et al.
patent: 5778233 (1998-07-01), Besaw et al.
patent: 5812811 (1998-09-01), Dubey et al.
patent: 5881307 (1999-03-01), Park et al.
patent: 5961630 (1999-10-01), Zaidi et al.
patent: 6115808 (2000-09-01), Arora
patent: 6128775 (2000-10-01), Chow et al.
patent: 6182284 (2001-01-01), Sreedhar et al.
patent: 6401195 (2002-06-01), Arora et al.
patent: 6434590 (2002-08-01), Blelloch et al.
patent: 6516462 (2003-02-01), Okunev et al.
patent: 6526572 (2003-02-01), Brauch et al.
patent: 6587940 (2003-07-01), Soltis et al.
patent: 6643767 (2003-11-01), Sato
patent: 6675380 (2004-01-01), McKinsey et al.
patent: 6877088 (2005-04-01), Dice
patent: 6948162 (2005-09-01), Kalogeropulos
patent: 7269827 (2007-09-01), Metzger
patent: 2003/0033510 (2003-02-01), Dice
patent: 2003/0101442 (2003-05-01), Wu
patent: 2003/0145313 (2003-07-01), Kalogeropulos
patent: 2003/0196197 (2003-10-01), Fu et al.
patent: 2004/0261068 (2004-12-01), Ju
patent: 2005/0039167 (2005-02-01), Fernandes et al.
patent: 2005/0055541 (2005-03-01), Aamodt et al.
patent: 2005/0138480 (2005-06-01), Srinivasan et al.
patent: 2005/0289530 (2005-12-01), Robison
patent: 2006/0090063 (2006-04-01), Theis
R.M. Tomasulo; An Efficient Algorithm for Exploiting Multiple Arithmetic Units; IBM Journal of Research and Development; Jan. 1967; pp. 25-33; vol. 11, No. 1.
James E. Smith; A Study of Branch Prediction Strategies; Proceedings of the 8thAnnual Symposium on Computer Architecture; May 12-14, 1981; pp. 135-148; IEEE Computer Society and ACM SIGARCH; Minneapolis, Minnesota.
J.R. Allen, Ken Kennedy, Carrie Porterfield, and Joe Warren; Conversion of Control Dependence to Data Dependence; Conference Record of the 10thAnnual ACM Symposium on Principles of Programming Languages; Jan. 24-26, 1988; pp. 177-1988; ACM SIGACT-SIGPLAN; Austin Texas.
Bowen Alpern, Mark N. Wegman, and F. Kenneth Zadeck; Detecting Equality of Variables in Programs; Conference Record of the 15thAnnual ACM Symposium on Principles of Programming Languages; Jan. 13-15, 1988; pp. 1-11; ACM Press.
Susan Howitz, Jan Prins, and Thomas Reps; On the Adequacy of Program Dependence Graphs for Representing Programs; Proceedings of the 15thAnnual ACM SIGACT-SIGPLAN Symposium on Principles of Programming Languages; Jan. 13-15, 1998; pp. 146-157; ACM Press.
Ron Cytron, Jeanne Ferrante, Barry K. Rosen, Mark N. Wegman, and F. Kenneth Zadeck; An Efficient Method of Computing Static Single Assignment Form; Conference Record of the 16thAnnual ACM Symposium on Principles of Programming Languages; Jan. 11-13, 1989; ACM SIGACT-SIGPLAN and ACM Press; Austin, Texas.
James R. Larus; SPIM S20: A MIPS R2000 Simulator; Technical Report CS-TS-90-966; 1990; pp. 1-25; Computer Science Department, University of Wisconsin Madison.
Robert A. Ballance, Arthur B. MacCabe, and Karl J. Ottenstein; The Program Dependence Web: A Representation Supporting Control-, Data-, and Demand-Driven Interpretation of Imperative Languages; Proceedings of the ACM SIGPLAN 1990 Conference on Programming Language Design and Implementation; Jun. 20-22, 1990; pp. 257-271; White Plains, New York.
Tse-Yu Yeh and Yale N. Patt; Two-level Adaptive Training Branch Prediction; Proceedings of the 24thAnnual International Symposium on Microarchitecture; Nov. 18-20, 1991; pp. 51-61; 1991; ACM SIGNMICRO and IEEE Computer Society TC-MICRO; Albuquerque, New Mexico.
Tse-Yu Yeh and Yale N. Patt; Alternative Implementations of Two-Level Adaptive Branch Prediction; Proceedings of the 19thAnnual International Symposium on Computer Architecture; May 19-21, 1992; pp. 124-134; Gold Coast, Australia.
Shien-Tai Pan, Kimming So, and Joseph T Rahmeh; Improving the Accuracy of Dynamic Branch Prediction Using Branch Correlation; Proceedings of the 5thInternational Conference on Architectural Support for Programming Languages and Operating Systems; Oct. 12-15, 1992; pp. 76-84.
Cecile Moura; Super DLX: A Generic Superscalar Simulator; ACAPS Technical Memo 64; Apr. 13, 1993; pp. 1-78; School of Computer Science, McGill University.
Scott McFarling; Combining Branch Predictors; WRL Technical Note TN-36; Jun. 1993; pp. 1-25; Digital Western Research Laboratory; Palo Alto, California.
Brad Calder and Dirk Grunwald; Fast & Accurate Instruction Fetch and Branch Prediction; Proceedings of the 21stAnnual International Symposium and Computer Architecture; Apr. 18-21, 1994; pp. 2-11; IEEE Computer Society TCCA and ACM SIGAECH Computer Architecture News.
Jens Knoop, Oliver Ruthing, and Bernhard Steffen; Partial Dead Code Elimination; Proceedings of the ACM SIGPLAN 1994 Conference on Programming Language Design and Implementation; Jun. 20-24, 1994; pp. 147-158; Orlando, Florida.
Po-Yung Chang, Eric Hao, Tse-Yu Yeh, and Yale Patt; Branch Classification: a New Mechanism for Improving Branch Predictor Performance; Proceedings of the 27thAnnual International Symposium on Microarchitecture; Nov. 1994; pp. 22-31; San Jose, California.
James R. Larus and Eric Schnarr; EEL: Machine-Independent Executable Editing; Proceedings of the ACM SIGPLAN 1995 Conference on Programming Language Design and Implementation, SIGPLAN Notices; Jun. 18-21, 1995; pp. 291-300; vol. 30, No. 6; La Jolla, California.
Po-Yung Chang, Marius Evers, and Yale N. Patt; Improving Branch Prediction Accuracy by Reducing Pattern History Table Interference; Proceedings of the 1996 Conference on Parallel Architectures and Compilation Techniques; Oct. 20-23, 1996; pp. 48-57; Boston, Massachusetts; Oct. 1996; pp. 48-57; IEE Computer Society Press.
Eric Rotenberg, Steve Bennett, and James E. Smith; Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching; Proceedings of the 29thAnnual International Symposium on Microarchitecture; Jan. 9-13, 1999; pp. 24-34; IEEE Computer Society TCCA; Paris, France.
Doug Burger and Todd M. Austin; The SimpleScalar Tool Set, Version 2.0; University of Wisconsin-Madison Computer Science Department Technical Report #1342; Jun. 1997; pp. 1-21.
Deszo Sima, Terence Fountain, and Peter Kacsuk; Advanced Computer Architectures: A Design Space Approach; 1997; pp. 559-563; Addison-Wesley.
Mikko H. Lipasti and John Paul Shen; Superspeculative Microarchitecture for Beyond AD 2000; IEEE CS Press Book (Companion CD); Sep. 1997; pp. 59-66; vol. 30, No. 9.
Yale N. Patt, Sanjay J. Patel, Marius Evers, Daniel H. Friendly, and Jared Stark; One Billion Transistors, One Uniprocessor, One Chip; IEE Computer; Sep. 1997; pp. 51-57; vol. 30, No. 9.
James E. Smith, and Sriram Vajapeyam; Trace Processors: Moving to Fourth-Generation Microarchitectures; Sep. 1997; pp. 68-74; IEEE Computer.
Eric Sprangle, Robert S. Chappell, Mitch Alsup, and Yale N. Patt; The Agree Predictor: A Mechanism for Reducing Negative Branch History Interference; Proceedings of the 24thInternational Conference on Computer Architecture; 1997; pp. 284-291; Denver, Colorado.
Rastislav Bodik and Rajiv Gupta; Partial Dead Code Elimination using Slicing Transformations; Proceedings of the ACM SIGPLAN 1997 Conference on Programming Language Design and Implementation, SIGPLAN Notices; Jun. 15-18, 1997; pp. 159-170; vol. 32, No. 6; Las Vegas, Nevada.
Rajiv Gupta, David A. Berson, and Jesse Z. Fang; Path Profile Guided Partial Dead Code Elimination Using Prediction; Proceedings of the 1997 International Conference on Parallel Architectures and Compilation Techniques; Nov. 10-14, 1997; pp. 102-113; IEEE Computer Society Press; San Fransisco, CA.
Daniel Homes Friendly, Sanjay Jeram Patel, and Yale N. Patt; Alternative Fetch and Issue Policies for the
Brophy Matthew J
Michael & Best & Friedrich LLP
Michigan Technological University
Zhen Wei Y
LandOfFree
Methods and systems for ordering instructions using future... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods and systems for ordering instructions using future..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and systems for ordering instructions using future... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4170865