Methods and systems for on-the-fly chip verification

Details Methods and systems for on-the-fly chip verification Methods and systems for on-the-fly chip verification

2011-08-09

2011-08-09

Lin, Sun J (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

C716S111000

Reexamination Certificate

active

07996801

ABSTRACT:
Methods and systems for on-the-fly chip verification method for tracking non-contiguous events. A method includes comparing a first search marker associated with a first check vector to a search key associated with an output vector of a design under test (DUT). The method also includes performing either: verifying a validity of the output vector when the first search marker equals the search key, or comparing a second search marker associated with a second check vector to the search key when the first search marker does not equal the search key.

REFERENCES:
patent: 4866654 (1989-09-01), Yamada
patent: 5425036 (1995-06-01), Liu et al.
patent: 5583430 (1996-12-01), Dinteman
patent: 6389379 (2002-05-01), Lin et al.
patent: 6477683 (2002-11-01), Killian et al.
patent: 6760888 (2004-07-01), Killian et al.
patent: 2004/0158788 (2004-08-01), Kaszynski et al.
patent: 2004/0216061 (2004-10-01), Floyd et al.
patent: 2007/0282556 (2007-12-01), Achkar et al.

Affiliated with

Also associated with

Rating

Methods and systems for on-the-fly chip verification does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods and systems for on-the-fly chip verification, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and systems for on-the-fly chip verification will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2724659