Patent
1996-04-29
1997-05-06
Robertson, David L.
395473, G06F 1300
Patent
active
056279930
ABSTRACT:
Methods and system for memory control in a computer system having a store-in cache. In response to main memory read or write requests from a secondary processor, data is transferred into a buffer during a snoop cycle to the store-in cache. The data in the buffer is merged with write-back data from the store-in cache in a write operation. Data is provided directly from the buffer to the secondary processor and to main memory in a read operation. The buffer can be placed on a memory controller of the computer system. A second store-in cache can also be used for main memory transfers.
REFERENCES:
patent: 4301505 (1981-11-01), Catiller et al.
patent: 4467419 (1984-08-01), Wakai
patent: 4539677 (1985-09-01), Lo
patent: 4630230 (1986-12-01), Sundet
patent: 4665481 (1987-05-01), Stonier et al.
patent: 4797813 (1989-01-01), Igarashi
patent: 4899275 (1990-02-01), Sachs et al.
patent: 5008816 (1991-04-01), Fogg, Jr. et al.
patent: 5010516 (1991-04-01), Oates
patent: 5014187 (1991-05-01), Debize et al.
patent: 5115411 (1992-05-01), Kass et al.
patent: 5117428 (1992-05-01), Jeppesen, III et al.
patent: 5233692 (1993-08-01), Gajjar et al.
patent: 5265237 (1993-11-01), Tobias et al.
patent: 5276849 (1994-01-01), Patel
patent: 5293603 (1994-03-01), MacWilliam et al.
Abato Richard P.
Greer William R.
Herring Christopher M.
International Business Machines - Corporation
Robertson David L.
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