Methods and systems for limiting supply bounce

Details Methods and systems for limiting supply bounce Methods and systems for limiting supply bounce

2003-08-12

2004-07-20

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Signal transmission integrity or spurious noise override

C326S087000

Reexamination Certificate

active

06765426

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to methods and systems for limiting supply bounce, such as power supply and/or ground bounce.
2. Background Art
There is a trend towards increasing the number of digital I/O pads on integrated circuits (“ICs”) to increase the integrated functionality and the number of bits of data processed. When multiple digital I/O pads switch simultaneously, currents in supply (power supply and/or ground) lines associated with the digital I/O pads tend to vary with time. Such transient current changes interact with supply line inductances to cause excursions in supply voltages. Thus supply (power supply and/or ground) voltages may oscillate above and/or below normal levels. This is called supply bounce or VDD/GND bounce. The increase of positive power supplies above normal operating levels and the decrease of ground below normal operating levels leads to relatively large amounts of current flow between the power supplies and pads. This limits the number of output pads which can simultaneously switch at any given time.
Methods and systems are therefore needed to limit supply bounce.
BRIEF SUMMARY OF THE INVENTION
The present invention is directed to methods and systems for limiting supply (power supply and/or ground) bounce. The invention enables control of output current drive dependent on changes in supply levels.
In accordance with the invention, gate drives of output drivers (e.g, PMOS and/or NMOS output drivers) are varied according to supply swings. For example, when a power supply, VDD, or a ground supply, GND, voltage increases above normal operating levels, the gate drive of a PMOS output driver is reduced. When a ground supply, GND, or VDD power supply voltage falls below normal operating levels, the gate drive of an NMOS output driver is reduced. This leads to reduced current flow between the supplies and the pad, thereby reducing supply bounce.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. It is noted that the invention is not limited to the specific embodiments described herein. Such embodiments are presented herein for illustrative purposes only. Additional embodiments will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein.


REFERENCES:
patent: 5786709 (1998-07-01), Kirsch et al.
patent: 6184729 (2001-02-01), Pasqualini
patent: 6396301 (2002-05-01), Wallace, Jr. et al.

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