Methods and systems for improving ESD clamp response time

Details Methods and systems for improving ESD clamp response time Methods and systems for improving ESD clamp response time

2001-07-13

2003-07-01

Han, Jessica (Department: 2838)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S091100, C361S113000

Reexamination Certificate

active

06587321

ABSTRACT:

STATEMENT REGARDING FEDERALLY-SPONSORED RESEARCH AND DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to electrostatic discharge (ESD) protection and, more particularly, to methods and systems for improving response times of ESD triggering and clamping circuitry.
2. Background Art
Terminal pads, such as those found on integrated circuits (ICs), couple IC circuitry to off-chip devices. If a terminal pad is subjected to ESD, the on-chip circuitry can be damaged. For example, ESD from human handling can be as high as 2000 Volts (V). ESD circuits are utilized to redirect ESD away from on-chip circuitry, typically to ground.
In some situations, a terminal pad has a voltage present during normal operations, such as a power supply voltage, which may adversely affect ESD circuit components. Protection circuits, such as diode strings, can be used to protect ESD circuit components from becoming over stressed during normal operations, for example, when the applied voltage exceeds the voltage rating of an ESD circuit component. A protection circuit inserted between a terminal pad and an ESD circuit reduces the voltage applied to the ESD circuit.
Delayed response time is a limitation in ESD circuit performance when an ESD protection circuit is implemented as a diode string. Typical ESD circuits contain a triggering circuit that activates a clamping circuit when the ESD threshold voltage is exceeded. The clamping circuit provides an immediate discharge path, typically to ground. However, when a diode string protection circuit is inserted between a terminal pad and an ESD triggering circuit, the triggering circuit does not respond to ESD events as quickly as it would without a diode string protection circuit. The response time of the triggering circuit is delayed since each diode in the diode string contributes a series parasitic resistance which, in combination with the diode forward voltage drop, reduces the applied voltage to the ESD triggering circuit. For example, if the threshold triggering voltage is 10 V, and each diode in a string of two diodes contributes a 0.7 V forward voltage drop and a 1 V parasitic resistance voltage drop, then the triggering circuit will not activate the clamp until the applied voltage reaches 13.4 V. The diode string causes the voltage on the triggering circuit to trail behind the voltage on the terminal pad.
Initial peaking is another limitation in ESD circuit performance when the ESD protection circuit is implemented with a diode string. An ESD event is characterized by a sharp increase in voltage. Because there is no discharge path until the ESD clamp is triggered, and the response time of the ESD triggering circuit will be delayed, the applied voltage will peak higher before the threshold triggering voltage is reached.
The delayed response time and initial peaking limitations of diode string protection circuits can be alleviated if larger area diodes, which have smaller substrate resistance, are employed. However, larger area diodes require more space on the IC, which is another limitation of the diode string protection circuit.
Methods and systems are needed that enable ESD triggering and clamping circuitry to respond quickly to ESD events, yet continue to protect ESD circuit components during normal operations.
BRIEF SUMMARY OF THE INVENTION
The present invention relates to electrostatic discharge (ESD) protection and, more particularly, to methods and systems for improving response times of ESD triggering and clamping circuitry.


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