Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1998-02-23
2001-09-11
Chin, Wellington (Department: 2664)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S242000, C370S412000, C370S458000, C714S011000, C714S030000, C714S043000, C714S805000
Reexamination Certificate
active
06289022
ABSTRACT:
TECHNICAL FIELD
The present invention relates, in general, to fault-tolerant computing. More particularly, the present invention relates to methods and systems for fault-tolerant transmission of information.
BACKGROUND OF THE INVENTION
The reliability of computer based applications continues to be an important consideration. Moreover, in fault-tolerant computing applications, insuring that a fault-tolerant pair of CPUs agree on a result, and transmit the agreed-to result to a network (e.g., an Ethernet bus) is a critical function. Several prior techniques have been used to perform this function, but all have certain deficiencies.
As an example, turning to
FIG. 1
, two CPUs, namely CPU A
11
and CPU B
13
redundantly process information. Communications subsystems A
15
and B
17
are attached to CPUs A
11
and B
13
, respectively. In one example, communications subsystems
15
and
17
may implement NodeBus/RS-232 communications. Each communications subsystem is attached to a synchronous bit comparator
19
using data and synchronization (e.g., RTS/CTS) connections. Comparator
19
performs a bit-by-bit comparison of the data streams, keeping them in sync using the synchronization connections. If the comparison agrees, the data is transmitted, bit-by-bit, to communications network
21
. Network data is commonly received by the two communications subsystems and verified by CPU operations.
The technique depicted in
FIG. 1
, and described above, requires precise bit synchronization between the two communications subsystems. This synchronization is implemented using the synchronization signaling between the communications subsystems and synchronous bit comparator
19
. Unfortunately, this technique is not generally applicable to many communications protocols because they do not provide facilities for the synchronization signaling required by this technique.
Turning to
FIG. 2
, a system employing another data comparison technique is depicted. In this example system, a message from CPU A
11
is formatted by its respective communications subsystem
15
and transmitted to communications subsystem
17
of CPU B
13
. Communications subsystem B
17
compares the message received from communications subsystem A to the message that it intends to transmit. If the comparison agrees, the message is transmitted to network
21
. One drawback to this technique is the requirement that each message be transmitted twice, with associated delays. That is, the message must first be transmitted from the first communications subsystem to the second communications subsystem, compared, and then transmitted from the second communications subsystem to the destination network.
The present invention is directed toward solutions to the above-described problems.
SUMMARY OF THE INVENTION
Briefly described, in a first aspect, the present invention includes a method of transmitting information to a network. The method includes receiving data from a first source into a first FIFO, and receiving data from a second source into a second FIFO. As data is received into the second FIFO, the data is transferred from the second FIFO to the network. When an end of message indication is detected in the received data, the first FIFO is compared to the second FIFO. If a miscompare occurs, the data transferred from the second FIFO to network is caused to be an error. Data exiting the first FIFO may be discarded throughout.
As an enhancement, upon miscompare, an error will be introduced into the data within the second FIFO prior to its transmission to the network. This error may include, for example, flipping at least one bit in the second FIFO, forcing at least one bit to a one or zero, or transmitting a protocol specific message abort pattern. Further, upon miscompare, transmission of the data from the second FIFO to the network may be prematurely terminated.
As a further enhancement, upon miscompare a signal may be sent to one or more of the first and second sources. The first and second sources may include at least one processor such that sending the signal may include generating an interrupt for the processor.
As yet another enhancement, a timer may be set upon initial receipt of data from the first source into the first FIFO. If the timer expires before comparing the FIFOs, a miscompare is declared and the transferred data from the second FIFO to network is caused to be an error.
The present invention also includes systems corresponding to the above-described methods. Particularly, in another aspect, the present invention includes a system for transmitting information to a network. The system includes first and second FIFOs for receiving data from first and second sources, respectively. Also, the system includes means for transferring data from the second FIFO to the network as data is received into the second FIFO. A means for detecting an end-of-message indication in the received data is also included in the system. Further, the system includes a means for comparing the first FIFO to the second FIFO upon detection of the end-of-message indication, and if a miscompare occurs transferred data from the second FIFO to the network is caused to be an error.
The present invention has several advantages and features associated therewith. The techniques disclosed represent a high-speed technique for insuring verification of the identity of redundant data streams prior to allowing successful transmission of them to a network. These techniques overcome the disadvantages of those used previously, in that dedicated signaling hardware is not needed for synchronization and the delays associated with store-compare-forward verification techniques are avoided.
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Gale Alan Andrew
Galpin Samuel
Chin Wellington
Foley Hoag & Eliot LLP
Liepmann W. Hugo
Oliver Kevin A.
Phan M.
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